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modified gpio pin

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This commit is contained in:
Fadhil Orbandi 2024-12-09 17:52:37 +01:00
parent 1558821e72
commit 4e11519c6d
2 changed files with 116 additions and 6 deletions
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109
include/sta/devices/stm32/mcu/STM32U5A5xx.hpp Normal file
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@ -0,0 +1,109 @@
#ifndef STA_CORE_STM32_MCU_STM32U5A5xx_HPP
#define STA_CORE_STM32_MCU_STM32U5A5xx_HPP
/**
* @defgroup sta_core_stm32_mcu_stm32f407xx STM32F407xx
* @ingroup sta_core_stm32_mcu
*
* @brief MCU configuration for the STM32F407xx family.
*/
#ifndef STM32U5A5xx
# error "MCU config incompatible"
#endif // STM32U5A5xx
#include <sta/devices/stm32/mcu/common.hpp>
// uart/CAN setup
#ifdef STA_STM32_ASEAG
# define STA_STM32_USART_HANDLE huart1
# define STA_STM32_CAN_HANDLE hcan1
#else
# ifdef STA_STM32_SWD_USART_IDX
# define STA_STM32_USART_HANDLE CONCAT(huart, STA_STM32_SWD_USART_IDX)
# endif // STA_STM32_SWD_USART_IDX
#endif // STA_STM32_SWD_USART_IDX
/**
* @ingroup sta_core_stm32_mcu_stm32U5A5xx
* @{
*/
// Peripheral clock mappings
//
// TIM to PCLK
#define STA_STM32_TIM_1_PCLK_IDX 2 /**< TIM1 to PCLK index */
#define STA_STM32_TIM_2_PCLK_IDX 1 /**< TIM2 to PCLK index */
#define STA_STM32_TIM_3_PCLK_IDX 1 /**< TIM3 to PCLK index */
#define STA_STM32_TIM_4_PCLK_IDX 1 /**< TIM4 to PCLK index */
#define STA_STM32_TIM_5_PCLK_IDX 1 /**< TIM5 to PCLK index */
#define STA_STM32_TIM_6_PCLK_IDX 1 /**< TIM6 to PCLK index */
#define STA_STM32_TIM_7_PCLK_IDX 1 /**< TIM7 to PCLK index */
#define STA_STM32_TIM_8_PCLK_IDX 2 /**< TIM8 to PCLK index */
#define STA_STM32_TIM_9_PCLK_IDX 2 /**< TIM9 to PCLK index */
#define STA_STM32_TIM_10_PCLK_IDX 2 /**< TIM10 to PCLK index */
#define STA_STM32_TIM_11_PCLK_IDX 2 /**< TIM11 to PCLK index */
#define STA_STM32_TIM_12_PCLK_IDX 1 /**< TIM12 to PCLK index */
#define STA_STM32_TIM_13_PCLK_IDX 1 /**< TIM13 to PCLK index */
#define STA_STM32_TIM_14_PCLK_IDX 1 /**< TIM14 to PCLK index */
// SPI to PCLK
#define STA_STM32_SPI_1_PCLK_IDX 2 /**< SPI1 to PCLK index */
#define STA_STM32_SPI_2_PCLK_IDX 1 /**< SPI2 to PCLK index */
#define STA_STM32_SPI_3_PCLK_IDX 1 /**< SPI3 to PCLK index */
// I2C to PCLK
#define STA_STM32_I2C_1_PCLK_IDX 1 /**< I2C1 to PCLK index */
#define STA_STM32_I2C_2_PCLK_IDX 1 /**< I2C2 to PCLK index */
#define STA_STM32_I2C_3_PCLK_IDX 1 /**< I2C3 to PCLK index */
// USART to PCLK
#define STA_STM32_USART_1_PCLK_IDX 2 /**< USART1 to PCLK index */
#define STA_STM32_USART_2_PCLK_IDX 1 /**< USART2 to PCLK index */
#define STA_STM32_USART_3_PCLK_IDX 1 /**< USART3 to PCLK index */
#define STA_STM32_USART_6_PCLK_IDX 2 /**< USART6 to PCLK index */
// prescaler from APBx to APBx timer clocks
#define STA_STM32_TIM_PCLK_1_PRESCALER 2 /**< PCLK1 has prescaler of 2 */
#define STA_STM32_TIM_PCLK_2_PRESCALER 2 /**< PCLK2 has prescaler of 1 */
// HAL handle mappings
//
#define STA_STM32_htim1_PCLK_IDX STA_STM32_TIM_1_PCLK_IDX /**< Mapping for HAL TIM1 to PCLK index */
#define STA_STM32_htim2_PCLK_IDX STA_STM32_TIM_2_PCLK_IDX /**< Mapping for HAL TIM2 to PCLK index */
#define STA_STM32_htim3_PCLK_IDX STA_STM32_TIM_3_PCLK_IDX /**< Mapping for HAL TIM3 to PCLK index */
#define STA_STM32_htim4_PCLK_IDX STA_STM32_TIM_4_PCLK_IDX /**< Mapping for HAL TIM4 to PCLK index */
#define STA_STM32_htim5_PCLK_IDX STA_STM32_TIM_5_PCLK_IDX /**< Mapping for HAL TIM5 to PCLK index */
#define STA_STM32_htim6_PCLK_IDX STA_STM32_TIM_6_PCLK_IDX /**< Mapping for HAL TIM6 to PCLK index */
#define STA_STM32_htim7_PCLK_IDX STA_STM32_TIM_7_PCLK_IDX /**< Mapping for HAL TIM7 to PCLK index */
#define STA_STM32_htim8_PCLK_IDX STA_STM32_TIM_8_PCLK_IDX /**< Mapping for HAL TIM8 to PCLK index */
#define STA_STM32_htim9_PCLK_IDX STA_STM32_TIM_9_PCLK_IDX /**< Mapping for HAL TIM9 to PCLK index */
#define STA_STM32_htim10_PCLK_IDX STA_STM32_TIM_10_PCLK_IDX /**< Mapping for HAL TIM10 to PCLK index */
#define STA_STM32_htim11_PCLK_IDX STA_STM32_TIM_11_PCLK_IDX /**< Mapping for HAL TIM11 to PCLK index */
#define STA_STM32_htim12_PCLK_IDX STA_STM32_TIM_12_PCLK_IDX /**< Mapping for HAL TIM12 to PCLK index */
#define STA_STM32_htim13_PCLK_IDX STA_STM32_TIM_13_PCLK_IDX /**< Mapping for HAL TIM13 to PCLK index */
// SPI to PCLK
#define STA_STM32_hspi1_PCLK_IDX STA_STM32_SPI_1_PCLK_IDX /**< Mapping for HAL SPI1 to PCLK index */
#define STA_STM32_hspi2_PCLK_IDX STA_STM32_SPI_2_PCLK_IDX /**< Mapping for HAL SPI2 to PCLK index */
#define STA_STM32_hspi3_PCLK_IDX STA_STM32_SPI_3_PCLK_IDX /**< Mapping for HAL SPI3 to PCLK index */
#define STA_STM32_hspi4_PCLK_IDX STA_STM32_SPI_4_PCLK_IDX /**< Mapping for HAL SPI4 to PCLK index */
#define STA_STM32_hspi5_PCLK_IDX STA_STM32_SPI_5_PCLK_IDX /**< Mapping for HAL SPI5 to PCLK index */
// I2C to PCLK
#define STA_STM32_hi2c1_PCLK_IDX STA_STM32_I2C_1_PCLK_IDX /**< Mapping for HAL I2C1 to PCLK index */
#define STA_STM32_hi2c2_PCLK_IDX STA_STM32_I2C_2_PCLK_IDX /**< Mapping for HAL I2C2 to PCLK index */
#define STA_STM32_h12c3_PCLK_IDX STA_STM32_I2C_3_PCLK_IDX /**< Mapping for HAL I2C3 to PCLK index */
// USART to PCLK
#define STA_STM32_husart1_PCLK_IDX STA_STM32_USART_1_PCLK_IDX /**< Mapping for HAL USART1 to PCLK index */
#define STA_STM32_husart2_PCLK_IDX STA_STM32_USART_2_PCLK_IDX /**< Mapping for HAL USART2 to PCLK index */
#define STA_STM32_husart3_PCLK_IDX STA_STM32_USART_3_PCLK_IDX /**< Mapping for HAL USART3 to PCLK index */
#define STA_STM32_husart6_PCLK_IDX STA_STM32_USART_6_PCLK_IDX /**< Mapping for HAL USART6 to PCLK index */
/** @} */
#endif // STA_CORE_STM32_MCU_STM32U5A5xx_HPP

13
src/devices/stm32/gpio_pin.cpp
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@ -43,23 +43,24 @@ namespace sta
{
uint32_t pin = gpioPin.getPin();
for (uint32_t i = 0; i < 8 * sizeof(pin); ++i)
for (uint32_t i = 0; i < 8 * sizeof(pin); ++i) //why 8?
{
uint32_t ioPos = 1U << i;
if (pin & ioPos)
{
// Check input mode
uint32_t mode = (gpioPin.getPort()->MODER >> (2U * i)) & GPIO_MODE;
if (mode != MODE_INPUT)
uint32_t mode = (gpioPin.getPort()->MODER >> (2U * i)) & 0x3UL; //GPIO_MODE to 0x3UL
//uint32_t mode = LL_GPIO_GetPinMode (gpioPin.getPort(), pin);
if (mode != 0x0UL) //MODE_INPUT to 0x0UL
{
return false;
}
// Is EXTI configured?
if (EXTI->IMR & ioPos)
if (EXTI->IMR1 & ioPos) //changed IMR to IMR1
{
bool rising = (EXTI->RTSR & ioPos);
bool falling = (EXTI->FTSR & ioPos);
bool rising = (EXTI->RTSR1 & ioPos); // changed RTSR to RTSR1
bool falling = (EXTI->FTSR1 & ioPos);
switch (edge)
{