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Updated clock prescaler, tested profiler and delayUs
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@@ -63,8 +63,13 @@
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#define STA_STM32_USART_2_PCLK_IDX 1 /**< USART2 to PCLK index 1 */
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#define STA_STM32_USART_6_PCLK_IDX 2 /**< USART6 to PCLK index 2 */
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// prescaler from APBx to APBx timer clocks
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#define STA_STM32_TIM_PCLK_1_PRESCALER 2 /**< PCLK1 has prescaler of 2 */
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#define STA_STM32_TIM_PCLK_2_PRESCALER 1 /**< PCLK2 has prescaler of 1 */
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// HAL handle mappings
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//
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// TIM to PCLK
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#define STA_STM32_htim1_PCLK_IDX STA_STM32_TIM_1_PCLK_IDX /**< HAL TIM1 to PCLK index */
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