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@CarlWachter
2024-01-06 17:17:40 +01:00
committed by CarlWachter
parent b3ed26e288
commit 16b9e6135c
26 changed files with 331 additions and 306 deletions
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87
include/sta/devices/stm32/mcu/STM32F411xE.hpp
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@@ -5,6 +5,11 @@
#ifndef STA_CORE_STM32_MCU_STM32F411xE_HPP
#define STA_CORE_STM32_MCU_STM32F411xE_HPP
/**
* @defgroup sta_core_stm32_mcu_stm32f411xe STM32F411xE
* @ingroup sta_core_stm32_mcu
* @brief Configuration for STM32F411xE family.
*/
#ifndef STM32F411xE
# error "MCU config incompatible"
@@ -13,67 +18,71 @@
#include <sta/devices/stm32/mcu/common.hpp>
/**
* @ingroup sta_core_stm32_mcu_stm32f411xe
* @{
*/
// Peripheral clock mappings
//
// TIM to PCLK
#define STA_STM32_TIM_1_PCLK_IDX 2
#define STA_STM32_TIM_2_PCLK_IDX 1
#define STA_STM32_TIM_3_PCLK_IDX 1
#define STA_STM32_TIM_4_PCLK_IDX 1
#define STA_STM32_TIM_5_PCLK_IDX 1
#define STA_STM32_TIM_9_PCLK_IDX 2
#define STA_STM32_TIM_10_PCLK_IDX 2
#define STA_STM32_TIM_11_PCLK_IDX 2
#define STA_STM32_TIM_1_PCLK_IDX 2 /**< TIM1 to PCLK index 2 */
#define STA_STM32_TIM_2_PCLK_IDX 1 /**< TIM2 to PCLK index 1 */
#define STA_STM32_TIM_3_PCLK_IDX 1 /**< TIM3 to PCLK index 1 */
#define STA_STM32_TIM_4_PCLK_IDX 1 /**< TIM4 to PCLK index 1 */
#define STA_STM32_TIM_5_PCLK_IDX 1 /**< TIM5 to PCLK index 1 */
#define STA_STM32_TIM_9_PCLK_IDX 2 /**< TIM9 to PCLK index 2 */
#define STA_STM32_TIM_10_PCLK_IDX 2 /**< TIM10 to PCLK index 2 */
#define STA_STM32_TIM_11_PCLK_IDX 2 /**< TIM11 to PCLK index 2 */
// SPI to PCLK
#define STA_STM32_SPI_1_PCLK_IDX 2
#define STA_STM32_SPI_2_PCLK_IDX 1
#define STA_STM32_SPI_3_PCLK_IDX 1
#define STA_STM32_SPI_4_PCLK_IDX 2
#define STA_STM32_SPI_5_PCLK_IDX 2
#define STA_STM32_SPI_1_PCLK_IDX 2 /**< SPI1 to PCLK index 2 */
#define STA_STM32_SPI_2_PCLK_IDX 1 /**< SPI2 to PCLK index 1 */
#define STA_STM32_SPI_3_PCLK_IDX 1 /**< SPI3 to PCLK index 1 */
#define STA_STM32_SPI_4_PCLK_IDX 2 /**< SPI4 to PCLK index 2 */
#define STA_STM32_SPI_5_PCLK_IDX 2 /**< SPI5 to PCLK index 2 */
// I2C to PCLK
#define STA_STM32_I2C_1_PCLK_IDX 1
#define STA_STM32_I2C_2_PCLK_IDX 1
#define STA_STM32_I2C_3_PCLK_IDX 1
#define STA_STM32_I2C_1_PCLK_IDX 1 /**< I2C1 to PCLK index 1 */
#define STA_STM32_I2C_2_PCLK_IDX 1 /**< I2C2 to PCLK index 1 */
#define STA_STM32_I2C_3_PCLK_IDX 1 /**< I2C3 to PCLK index 1 */
// USART to PCLK
#define STA_STM32_USART_1_PCLK_IDX 2
#define STA_STM32_USART_2_PCLK_IDX 1
#define STA_STM32_USART_6_PCLK_IDX 2
#define STA_STM32_USART_1_PCLK_IDX 2 /**< USART1 to PCLK index 2 */
#define STA_STM32_USART_2_PCLK_IDX 1 /**< USART2 to PCLK index 1 */
#define STA_STM32_USART_6_PCLK_IDX 2 /**< USART6 to PCLK index 2 */
// HAL handle mappings
//
// TIM to PCLK
#define STA_STM32_htim1_PCLK_IDX STA_STM32_TIM_1_PCLK_IDX
#define STA_STM32_htim2_PCLK_IDX STA_STM32_TIM_2_PCLK_IDX
#define STA_STM32_htim3_PCLK_IDX STA_STM32_TIM_3_PCLK_IDX
#define STA_STM32_htim4_PCLK_IDX STA_STM32_TIM_4_PCLK_IDX
#define STA_STM32_htim5_PCLK_IDX STA_STM32_TIM_5_PCLK_IDX
#define STA_STM32_htim9_PCLK_IDX STA_STM32_TIM_9_PCLK_IDX
#define STA_STM32_htim10_PCLK_IDX STA_STM32_TIM_10_PCLK_IDX
#define STA_STM32_htim11_PCLK_IDX STA_STM32_TIM_11_PCLK_IDX
#define STA_STM32_htim1_PCLK_IDX STA_STM32_TIM_1_PCLK_IDX /**< HAL TIM1 to PCLK index */
#define STA_STM32_htim2_PCLK_IDX STA_STM32_TIM_2_PCLK_IDX /**< HAL TIM2 to PCLK index */
#define STA_STM32_htim3_PCLK_IDX STA_STM32_TIM_3_PCLK_IDX /**< HAL TIM3 to PCLK index */
#define STA_STM32_htim4_PCLK_IDX STA_STM32_TIM_4_PCLK_IDX /**< HAL TIM4 to PCLK index */
#define STA_STM32_htim5_PCLK_IDX STA_STM32_TIM_5_PCLK_IDX /**< HAL TIM5 to PCLK index */
#define STA_STM32_htim9_PCLK_IDX STA_STM32_TIM_9_PCLK_IDX /**< HAL TIM9 to PCLK index */
#define STA_STM32_htim10_PCLK_IDX STA_STM32_TIM_10_PCLK_IDX /**< HAL TIM10 to PCLK index */
#define STA_STM32_htim11_PCLK_IDX STA_STM32_TIM_11_PCLK_IDX /**< HAL TIM11 to PCLK index */
// SPI to PCLK
#define STA_STM32_hspi1_PCLK_IDX STA_STM32_SPI_1_PCLK_IDX
#define STA_STM32_hspi2_PCLK_IDX STA_STM32_SPI_2_PCLK_IDX
#define STA_STM32_hspi3_PCLK_IDX STA_STM32_SPI_3_PCLK_IDX
#define STA_STM32_hspi4_PCLK_IDX STA_STM32_SPI_4_PCLK_IDX
#define STA_STM32_hspi5_PCLK_IDX STA_STM32_SPI_5_PCLK_IDX
#define STA_STM32_hspi1_PCLK_IDX STA_STM32_SPI_1_PCLK_IDX /**< HAL SPI1 to PCLK index */
#define STA_STM32_hspi2_PCLK_IDX STA_STM32_SPI_2_PCLK_IDX /**< HAL SPI2 to PCLK index */
#define STA_STM32_hspi3_PCLK_IDX STA_STM32_SPI_3_PCLK_IDX /**< HAL SPI3 to PCLK index */
#define STA_STM32_hspi4_PCLK_IDX STA_STM32_SPI_4_PCLK_IDX /**< HAL SPI4 to PCLK index */
#define STA_STM32_hspi5_PCLK_IDX STA_STM32_SPI_5_PCLK_IDX /**< HAL SPI5 to PCLK index */
// I2C to PCLK
#define STA_STM32_hi2c1_PCLK_IDX STA_STM32_I2C_1_PCLK_IDX
#define STA_STM32_hi2c2_PCLK_IDX STA_STM32_I2C_2_PCLK_IDX
#define STA_STM32_h12c3_PCLK_IDX STA_STM32_I2C_3_PCLK_IDX
#define STA_STM32_hi2c1_PCLK_IDX STA_STM32_I2C_1_PCLK_IDX /**< HAL I2C1 to PCLK index */
#define STA_STM32_hi2c2_PCLK_IDX STA_STM32_I2C_2_PCLK_IDX /**< HAL I2C2 to PCLK index */
#define STA_STM32_h12c3_PCLK_IDX STA_STM32_I2C_3_PCLK_IDX /**< HAL I2C3 to PCLK index */
// USART to PCLK
#define STA_STM32_husart1_PCLK_IDX STA_STM32_USART_1_PCLK_IDX
#define STA_STM32_husart2_PCLK_IDX STA_STM32_USART_2_PCLK_IDX
#define STA_STM32_husart6_PCLK_IDX STA_STM32_USART_6_PCLK_IDX
#define STA_STM32_husart1_PCLK_IDX STA_STM32_USART_1_PCLK_IDX /**< HAL USART1 to PCLK index */
#define STA_STM32_husart2_PCLK_IDX STA_STM32_USART_2_PCLK_IDX /**< HAL USART2 to PCLK index */
#define STA_STM32_husart6_PCLK_IDX STA_STM32_USART_6_PCLK_IDX /**< HAL USART6 to PCLK index */
/** @} */
#endif // STA_CORE_STM32_MCU_STM32F411xE_HPP