mirror of
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Updated: Doxygen Documentation
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@CarlWachter
committed by
CarlWachter
CarlWachter
parent
b3ed26e288
commit
16b9e6135c
@@ -1,6 +1,13 @@
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#ifndef STA_CORE_STM32_MCU_STM32F407xx_HPP
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#define STA_CORE_STM32_MCU_STM32F407xx_HPP
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/**
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* @defgroup sta_core_stm32_mcu_stm32f407xx STM32F407xx
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* @ingroup sta_core_stm32_mcu
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*
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* @brief MCU configuration for the STM32F407xx family.
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*/
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#ifndef STM32F407xx
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# error "MCU config incompatible"
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#endif // STM32F407xx
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@@ -16,76 +23,81 @@
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# endif // STA_STM32_SWD_USART_IDX
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#endif // STA_STM32_SWD_USART_IDX
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/**
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* @ingroup sta_core_stm32_mcu_stm32f407xx
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* @{
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*/
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// Peripheral clock mappings
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//
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// TIM to PCLK
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#define STA_STM32_TIM_1_PCLK_IDX 2
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#define STA_STM32_TIM_2_PCLK_IDX 1
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#define STA_STM32_TIM_3_PCLK_IDX 1
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#define STA_STM32_TIM_4_PCLK_IDX 1
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#define STA_STM32_TIM_5_PCLK_IDX 1
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#define STA_STM32_TIM_6_PCLK_IDX 1
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#define STA_STM32_TIM_7_PCLK_IDX 1
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#define STA_STM32_TIM_8_PCLK_IDX 2
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#define STA_STM32_TIM_9_PCLK_IDX 2
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#define STA_STM32_TIM_10_PCLK_IDX 2
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#define STA_STM32_TIM_11_PCLK_IDX 2
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#define STA_STM32_TIM_12_PCLK_IDX 1
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#define STA_STM32_TIM_13_PCLK_IDX 1
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#define STA_STM32_TIM_14_PCLK_IDX 1
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#define STA_STM32_TIM_1_PCLK_IDX 2 /**< TIM1 to PCLK index */
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#define STA_STM32_TIM_2_PCLK_IDX 1 /**< TIM2 to PCLK index */
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#define STA_STM32_TIM_3_PCLK_IDX 1 /**< TIM3 to PCLK index */
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#define STA_STM32_TIM_4_PCLK_IDX 1 /**< TIM4 to PCLK index */
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#define STA_STM32_TIM_5_PCLK_IDX 1 /**< TIM5 to PCLK index */
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#define STA_STM32_TIM_6_PCLK_IDX 1 /**< TIM6 to PCLK index */
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#define STA_STM32_TIM_7_PCLK_IDX 1 /**< TIM7 to PCLK index */
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#define STA_STM32_TIM_8_PCLK_IDX 2 /**< TIM8 to PCLK index */
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#define STA_STM32_TIM_9_PCLK_IDX 2 /**< TIM9 to PCLK index */
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#define STA_STM32_TIM_10_PCLK_IDX 2 /**< TIM10 to PCLK index */
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#define STA_STM32_TIM_11_PCLK_IDX 2 /**< TIM11 to PCLK index */
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#define STA_STM32_TIM_12_PCLK_IDX 1 /**< TIM12 to PCLK index */
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#define STA_STM32_TIM_13_PCLK_IDX 1 /**< TIM13 to PCLK index */
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#define STA_STM32_TIM_14_PCLK_IDX 1 /**< TIM14 to PCLK index */
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// SPI to PCLK
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#define STA_STM32_SPI_1_PCLK_IDX 2
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#define STA_STM32_SPI_2_PCLK_IDX 1
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#define STA_STM32_SPI_3_PCLK_IDX 1
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#define STA_STM32_SPI_1_PCLK_IDX 2 /**< SPI1 to PCLK index */
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#define STA_STM32_SPI_2_PCLK_IDX 1 /**< SPI2 to PCLK index */
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#define STA_STM32_SPI_3_PCLK_IDX 1 /**< SPI3 to PCLK index */
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// I2C to PCLK
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#define STA_STM32_I2C_1_PCLK_IDX 1
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#define STA_STM32_I2C_2_PCLK_IDX 1
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#define STA_STM32_I2C_3_PCLK_IDX 1
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#define STA_STM32_I2C_1_PCLK_IDX 1 /**< I2C1 to PCLK index */
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#define STA_STM32_I2C_2_PCLK_IDX 1 /**< I2C2 to PCLK index */
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#define STA_STM32_I2C_3_PCLK_IDX 1 /**< I2C3 to PCLK index */
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// USART to PCLK
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#define STA_STM32_USART_1_PCLK_IDX 2
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#define STA_STM32_USART_2_PCLK_IDX 1
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#define STA_STM32_USART_3_PCLK_IDX 1
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#define STA_STM32_USART_6_PCLK_IDX 2
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#define STA_STM32_USART_1_PCLK_IDX 2 /**< USART1 to PCLK index */
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#define STA_STM32_USART_2_PCLK_IDX 1 /**< USART2 to PCLK index */
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#define STA_STM32_USART_3_PCLK_IDX 1 /**< USART3 to PCLK index */
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#define STA_STM32_USART_6_PCLK_IDX 2 /**< USART6 to PCLK index */
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// HAL handle mappings
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//
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#define STA_STM32_htim1_PCLK_IDX STA_STM32_TIM_1_PCLK_IDX
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#define STA_STM32_htim2_PCLK_IDX STA_STM32_TIM_2_PCLK_IDX
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#define STA_STM32_htim3_PCLK_IDX STA_STM32_TIM_3_PCLK_IDX
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#define STA_STM32_htim4_PCLK_IDX STA_STM32_TIM_4_PCLK_IDX
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#define STA_STM32_htim5_PCLK_IDX STA_STM32_TIM_5_PCLK_IDX
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#define STA_STM32_htim6_PCLK_IDX STA_STM32_TIM_6_PCLK_IDX
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#define STA_STM32_htim7_PCLK_IDX STA_STM32_TIM_7_PCLK_IDX
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#define STA_STM32_htim8_PCLK_IDX STA_STM32_TIM_8_PCLK_IDX
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#define STA_STM32_htim9_PCLK_IDX STA_STM32_TIM_9_PCLK_IDX
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#define STA_STM32_htim10_PCLK_IDX STA_STM32_TIM_10_PCLK_IDX
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#define STA_STM32_htim11_PCLK_IDX STA_STM32_TIM_11_PCLK_IDX
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#define STA_STM32_htim12_PCLK_IDX STA_STM32_TIM_12_PCLK_IDX
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#define STA_STM32_htim13_PCLK_IDX STA_STM32_TIM_13_PCLK_IDX
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#define STA_STM32_htim1_PCLK_IDX STA_STM32_TIM_1_PCLK_IDX /**< Mapping for HAL TIM1 to PCLK index */
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#define STA_STM32_htim2_PCLK_IDX STA_STM32_TIM_2_PCLK_IDX /**< Mapping for HAL TIM2 to PCLK index */
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#define STA_STM32_htim3_PCLK_IDX STA_STM32_TIM_3_PCLK_IDX /**< Mapping for HAL TIM3 to PCLK index */
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#define STA_STM32_htim4_PCLK_IDX STA_STM32_TIM_4_PCLK_IDX /**< Mapping for HAL TIM4 to PCLK index */
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#define STA_STM32_htim5_PCLK_IDX STA_STM32_TIM_5_PCLK_IDX /**< Mapping for HAL TIM5 to PCLK index */
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#define STA_STM32_htim6_PCLK_IDX STA_STM32_TIM_6_PCLK_IDX /**< Mapping for HAL TIM6 to PCLK index */
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#define STA_STM32_htim7_PCLK_IDX STA_STM32_TIM_7_PCLK_IDX /**< Mapping for HAL TIM7 to PCLK index */
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#define STA_STM32_htim8_PCLK_IDX STA_STM32_TIM_8_PCLK_IDX /**< Mapping for HAL TIM8 to PCLK index */
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#define STA_STM32_htim9_PCLK_IDX STA_STM32_TIM_9_PCLK_IDX /**< Mapping for HAL TIM9 to PCLK index */
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#define STA_STM32_htim10_PCLK_IDX STA_STM32_TIM_10_PCLK_IDX /**< Mapping for HAL TIM10 to PCLK index */
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#define STA_STM32_htim11_PCLK_IDX STA_STM32_TIM_11_PCLK_IDX /**< Mapping for HAL TIM11 to PCLK index */
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#define STA_STM32_htim12_PCLK_IDX STA_STM32_TIM_12_PCLK_IDX /**< Mapping for HAL TIM12 to PCLK index */
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#define STA_STM32_htim13_PCLK_IDX STA_STM32_TIM_13_PCLK_IDX /**< Mapping for HAL TIM13 to PCLK index */
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// SPI to PCLK
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#define STA_STM32_hspi1_PCLK_IDX STA_STM32_SPI_1_PCLK_IDX
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#define STA_STM32_hspi2_PCLK_IDX STA_STM32_SPI_2_PCLK_IDX
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#define STA_STM32_hspi3_PCLK_IDX STA_STM32_SPI_3_PCLK_IDX
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#define STA_STM32_hspi4_PCLK_IDX STA_STM32_SPI_4_PCLK_IDX
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#define STA_STM32_hspi5_PCLK_IDX STA_STM32_SPI_5_PCLK_IDX
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#define STA_STM32_hspi1_PCLK_IDX STA_STM32_SPI_1_PCLK_IDX /**< Mapping for HAL SPI1 to PCLK index */
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#define STA_STM32_hspi2_PCLK_IDX STA_STM32_SPI_2_PCLK_IDX /**< Mapping for HAL SPI2 to PCLK index */
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#define STA_STM32_hspi3_PCLK_IDX STA_STM32_SPI_3_PCLK_IDX /**< Mapping for HAL SPI3 to PCLK index */
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#define STA_STM32_hspi4_PCLK_IDX STA_STM32_SPI_4_PCLK_IDX /**< Mapping for HAL SPI4 to PCLK index */
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#define STA_STM32_hspi5_PCLK_IDX STA_STM32_SPI_5_PCLK_IDX /**< Mapping for HAL SPI5 to PCLK index */
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// I2C to PCLK
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#define STA_STM32_hi2c1_PCLK_IDX STA_STM32_I2C_1_PCLK_IDX
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#define STA_STM32_hi2c2_PCLK_IDX STA_STM32_I2C_2_PCLK_IDX
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#define STA_STM32_h12c3_PCLK_IDX STA_STM32_I2C_3_PCLK_IDX
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#define STA_STM32_hi2c1_PCLK_IDX STA_STM32_I2C_1_PCLK_IDX /**< Mapping for HAL I2C1 to PCLK index */
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#define STA_STM32_hi2c2_PCLK_IDX STA_STM32_I2C_2_PCLK_IDX /**< Mapping for HAL I2C2 to PCLK index */
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#define STA_STM32_h12c3_PCLK_IDX STA_STM32_I2C_3_PCLK_IDX /**< Mapping for HAL I2C3 to PCLK index */
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// USART to PCLK
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#define STA_STM32_husart1_PCLK_IDX STA_STM32_USART_1_PCLK_IDX
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#define STA_STM32_husart2_PCLK_IDX STA_STM32_USART_2_PCLK_IDX
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#define STA_STM32_husart3_PCLK_IDX STA_STM32_USART_3_PCLK_IDX
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#define STA_STM32_husart6_PCLK_IDX STA_STM32_USART_6_PCLK_IDX
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#define STA_STM32_husart1_PCLK_IDX STA_STM32_USART_1_PCLK_IDX /**< Mapping for HAL USART1 to PCLK index */
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#define STA_STM32_husart2_PCLK_IDX STA_STM32_USART_2_PCLK_IDX /**< Mapping for HAL USART2 to PCLK index */
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#define STA_STM32_husart3_PCLK_IDX STA_STM32_USART_3_PCLK_IDX /**< Mapping for HAL USART3 to PCLK index */
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#define STA_STM32_husart6_PCLK_IDX STA_STM32_USART_6_PCLK_IDX /**< Mapping for HAL USART6 to PCLK index */
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/** @} */
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#endif // STA_CORE_STM32_MCU_STM32F407xx_HPP
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@@ -5,6 +5,11 @@
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#ifndef STA_CORE_STM32_MCU_STM32F411xE_HPP
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#define STA_CORE_STM32_MCU_STM32F411xE_HPP
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/**
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* @defgroup sta_core_stm32_mcu_stm32f411xe STM32F411xE
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* @ingroup sta_core_stm32_mcu
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* @brief Configuration for STM32F411xE family.
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*/
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#ifndef STM32F411xE
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# error "MCU config incompatible"
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@@ -13,67 +18,71 @@
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#include <sta/devices/stm32/mcu/common.hpp>
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/**
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* @ingroup sta_core_stm32_mcu_stm32f411xe
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* @{
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*/
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// Peripheral clock mappings
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//
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// TIM to PCLK
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#define STA_STM32_TIM_1_PCLK_IDX 2
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#define STA_STM32_TIM_2_PCLK_IDX 1
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#define STA_STM32_TIM_3_PCLK_IDX 1
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#define STA_STM32_TIM_4_PCLK_IDX 1
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#define STA_STM32_TIM_5_PCLK_IDX 1
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#define STA_STM32_TIM_9_PCLK_IDX 2
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#define STA_STM32_TIM_10_PCLK_IDX 2
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#define STA_STM32_TIM_11_PCLK_IDX 2
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#define STA_STM32_TIM_1_PCLK_IDX 2 /**< TIM1 to PCLK index 2 */
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#define STA_STM32_TIM_2_PCLK_IDX 1 /**< TIM2 to PCLK index 1 */
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#define STA_STM32_TIM_3_PCLK_IDX 1 /**< TIM3 to PCLK index 1 */
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#define STA_STM32_TIM_4_PCLK_IDX 1 /**< TIM4 to PCLK index 1 */
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#define STA_STM32_TIM_5_PCLK_IDX 1 /**< TIM5 to PCLK index 1 */
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#define STA_STM32_TIM_9_PCLK_IDX 2 /**< TIM9 to PCLK index 2 */
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#define STA_STM32_TIM_10_PCLK_IDX 2 /**< TIM10 to PCLK index 2 */
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#define STA_STM32_TIM_11_PCLK_IDX 2 /**< TIM11 to PCLK index 2 */
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// SPI to PCLK
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#define STA_STM32_SPI_1_PCLK_IDX 2
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#define STA_STM32_SPI_2_PCLK_IDX 1
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#define STA_STM32_SPI_3_PCLK_IDX 1
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#define STA_STM32_SPI_4_PCLK_IDX 2
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#define STA_STM32_SPI_5_PCLK_IDX 2
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#define STA_STM32_SPI_1_PCLK_IDX 2 /**< SPI1 to PCLK index 2 */
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#define STA_STM32_SPI_2_PCLK_IDX 1 /**< SPI2 to PCLK index 1 */
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#define STA_STM32_SPI_3_PCLK_IDX 1 /**< SPI3 to PCLK index 1 */
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#define STA_STM32_SPI_4_PCLK_IDX 2 /**< SPI4 to PCLK index 2 */
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#define STA_STM32_SPI_5_PCLK_IDX 2 /**< SPI5 to PCLK index 2 */
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// I2C to PCLK
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#define STA_STM32_I2C_1_PCLK_IDX 1
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#define STA_STM32_I2C_2_PCLK_IDX 1
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#define STA_STM32_I2C_3_PCLK_IDX 1
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#define STA_STM32_I2C_1_PCLK_IDX 1 /**< I2C1 to PCLK index 1 */
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#define STA_STM32_I2C_2_PCLK_IDX 1 /**< I2C2 to PCLK index 1 */
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#define STA_STM32_I2C_3_PCLK_IDX 1 /**< I2C3 to PCLK index 1 */
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// USART to PCLK
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#define STA_STM32_USART_1_PCLK_IDX 2
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#define STA_STM32_USART_2_PCLK_IDX 1
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#define STA_STM32_USART_6_PCLK_IDX 2
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#define STA_STM32_USART_1_PCLK_IDX 2 /**< USART1 to PCLK index 2 */
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#define STA_STM32_USART_2_PCLK_IDX 1 /**< USART2 to PCLK index 1 */
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#define STA_STM32_USART_6_PCLK_IDX 2 /**< USART6 to PCLK index 2 */
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// HAL handle mappings
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//
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// TIM to PCLK
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#define STA_STM32_htim1_PCLK_IDX STA_STM32_TIM_1_PCLK_IDX
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#define STA_STM32_htim2_PCLK_IDX STA_STM32_TIM_2_PCLK_IDX
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#define STA_STM32_htim3_PCLK_IDX STA_STM32_TIM_3_PCLK_IDX
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#define STA_STM32_htim4_PCLK_IDX STA_STM32_TIM_4_PCLK_IDX
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#define STA_STM32_htim5_PCLK_IDX STA_STM32_TIM_5_PCLK_IDX
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#define STA_STM32_htim9_PCLK_IDX STA_STM32_TIM_9_PCLK_IDX
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#define STA_STM32_htim10_PCLK_IDX STA_STM32_TIM_10_PCLK_IDX
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#define STA_STM32_htim11_PCLK_IDX STA_STM32_TIM_11_PCLK_IDX
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#define STA_STM32_htim1_PCLK_IDX STA_STM32_TIM_1_PCLK_IDX /**< HAL TIM1 to PCLK index */
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#define STA_STM32_htim2_PCLK_IDX STA_STM32_TIM_2_PCLK_IDX /**< HAL TIM2 to PCLK index */
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#define STA_STM32_htim3_PCLK_IDX STA_STM32_TIM_3_PCLK_IDX /**< HAL TIM3 to PCLK index */
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#define STA_STM32_htim4_PCLK_IDX STA_STM32_TIM_4_PCLK_IDX /**< HAL TIM4 to PCLK index */
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#define STA_STM32_htim5_PCLK_IDX STA_STM32_TIM_5_PCLK_IDX /**< HAL TIM5 to PCLK index */
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#define STA_STM32_htim9_PCLK_IDX STA_STM32_TIM_9_PCLK_IDX /**< HAL TIM9 to PCLK index */
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#define STA_STM32_htim10_PCLK_IDX STA_STM32_TIM_10_PCLK_IDX /**< HAL TIM10 to PCLK index */
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#define STA_STM32_htim11_PCLK_IDX STA_STM32_TIM_11_PCLK_IDX /**< HAL TIM11 to PCLK index */
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// SPI to PCLK
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#define STA_STM32_hspi1_PCLK_IDX STA_STM32_SPI_1_PCLK_IDX
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#define STA_STM32_hspi2_PCLK_IDX STA_STM32_SPI_2_PCLK_IDX
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#define STA_STM32_hspi3_PCLK_IDX STA_STM32_SPI_3_PCLK_IDX
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#define STA_STM32_hspi4_PCLK_IDX STA_STM32_SPI_4_PCLK_IDX
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#define STA_STM32_hspi5_PCLK_IDX STA_STM32_SPI_5_PCLK_IDX
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#define STA_STM32_hspi1_PCLK_IDX STA_STM32_SPI_1_PCLK_IDX /**< HAL SPI1 to PCLK index */
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#define STA_STM32_hspi2_PCLK_IDX STA_STM32_SPI_2_PCLK_IDX /**< HAL SPI2 to PCLK index */
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#define STA_STM32_hspi3_PCLK_IDX STA_STM32_SPI_3_PCLK_IDX /**< HAL SPI3 to PCLK index */
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#define STA_STM32_hspi4_PCLK_IDX STA_STM32_SPI_4_PCLK_IDX /**< HAL SPI4 to PCLK index */
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#define STA_STM32_hspi5_PCLK_IDX STA_STM32_SPI_5_PCLK_IDX /**< HAL SPI5 to PCLK index */
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// I2C to PCLK
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#define STA_STM32_hi2c1_PCLK_IDX STA_STM32_I2C_1_PCLK_IDX
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#define STA_STM32_hi2c2_PCLK_IDX STA_STM32_I2C_2_PCLK_IDX
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#define STA_STM32_h12c3_PCLK_IDX STA_STM32_I2C_3_PCLK_IDX
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#define STA_STM32_hi2c1_PCLK_IDX STA_STM32_I2C_1_PCLK_IDX /**< HAL I2C1 to PCLK index */
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#define STA_STM32_hi2c2_PCLK_IDX STA_STM32_I2C_2_PCLK_IDX /**< HAL I2C2 to PCLK index */
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#define STA_STM32_h12c3_PCLK_IDX STA_STM32_I2C_3_PCLK_IDX /**< HAL I2C3 to PCLK index */
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// USART to PCLK
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#define STA_STM32_husart1_PCLK_IDX STA_STM32_USART_1_PCLK_IDX
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#define STA_STM32_husart2_PCLK_IDX STA_STM32_USART_2_PCLK_IDX
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#define STA_STM32_husart6_PCLK_IDX STA_STM32_USART_6_PCLK_IDX
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#define STA_STM32_husart1_PCLK_IDX STA_STM32_USART_1_PCLK_IDX /**< HAL USART1 to PCLK index */
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#define STA_STM32_husart2_PCLK_IDX STA_STM32_USART_2_PCLK_IDX /**< HAL USART2 to PCLK index */
|
||||
#define STA_STM32_husart6_PCLK_IDX STA_STM32_USART_6_PCLK_IDX /**< HAL USART6 to PCLK index */
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif // STA_CORE_STM32_MCU_STM32F411xE_HPP
|
||||
|
||||
@@ -1,6 +1,11 @@
|
||||
#ifndef STA_CORE_STM32_MCU_TEMPLATE_HPP
|
||||
#define STA_CORE_STM32_MCU_TEMPLATE_HPP
|
||||
|
||||
/**
|
||||
* @defgroup sta_core_stm32_mcu STM32 MCUs
|
||||
* @ingroup sta_core_stm32
|
||||
*/
|
||||
|
||||
#ifndef STM32_YOUR_MCU_xx
|
||||
# error "MCU config incompatible"
|
||||
#endif // STM32_YOUR_MCU_xx
|
||||
|
||||
Reference in New Issue
Block a user