408 lines
6.6 KiB
C
408 lines
6.6 KiB
C
/*
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* Copyright © 2008 Keith Packard <keithp@keithp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*/
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#include <stdint.h>
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/*
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* Validate the SPI-connected EEPROM
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*/
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sfr at 0x80 P0;
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sfr at 0x90 P1;
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sfr at 0xA0 P2;
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sfr at 0xC6 CLKCON;
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sfr at 0xbe SLEEP;
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# define SLEEP_USB_EN (1 << 7)
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# define SLEEP_XOSC_STB (1 << 6)
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sfr at 0xF1 PERCFG;
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#define PERCFG_T1CFG_ALT_1 (0 << 6)
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#define PERCFG_T1CFG_ALT_2 (1 << 6)
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#define PERCFG_T3CFG_ALT_1 (0 << 5)
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#define PERCFG_T3CFG_ALT_2 (1 << 5)
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#define PERCFG_T4CFG_ALT_1 (0 << 4)
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#define PERCFG_T4CFG_ALT_2 (1 << 4)
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#define PERCFG_U1CFG_ALT_1 (0 << 1)
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#define PERCFG_U1CFG_ALT_2 (1 << 1)
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#define PERCFG_U0CFG_ALT_1 (0 << 0)
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#define PERCFG_U0CFG_ALT_2 (1 << 0)
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sfr at 0xF2 ADCCFG;
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sfr at 0xF3 P0SEL;
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sfr at 0xF4 P1SEL;
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sfr at 0xF5 P2SEL;
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sfr at 0xFD P0DIR;
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sfr at 0xFE P1DIR;
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sfr at 0xFF P2DIR;
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sfr at 0x8F P0INP;
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sfr at 0xF6 P1INP;
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sfr at 0xF7 P2INP;
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sfr at 0x89 P0IFG;
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sfr at 0x8A P1IFG;
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sfr at 0x8B P2IFG;
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sbit at 0x90 P1_0;
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sbit at 0x91 P1_1;
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sbit at 0x92 P1_2;
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sbit at 0x93 P1_3;
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sbit at 0x94 P1_4;
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sbit at 0x95 P1_5;
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sbit at 0x96 P1_6;
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sbit at 0x97 P1_7;
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/*
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* UART registers
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*/
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sfr at 0x86 U0CSR;
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sfr at 0xF8 U1CSR;
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# define UxCSR_MODE_UART (1 << 7)
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# define UxCSR_MODE_SPI (0 << 7)
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# define UxCSR_RE (1 << 6)
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# define UxCSR_SLAVE (1 << 5)
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# define UxCSR_MASTER (0 << 5)
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# define UxCSR_FE (1 << 4)
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# define UxCSR_ERR (1 << 3)
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# define UxCSR_RX_BYTE (1 << 2)
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# define UxCSR_TX_BYTE (1 << 1)
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# define UxCSR_ACTIVE (1 << 0)
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sfr at 0xc4 U0UCR;
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sfr at 0xfb U1UCR;
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sfr at 0xc5 U0GCR;
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sfr at 0xfc U1GCR;
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# define UxGCR_CPOL_NEGATIVE (0 << 7)
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# define UxGCR_CPOL_POSITIVE (1 << 7)
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# define UxGCR_CPHA_FIRST_EDGE (0 << 6)
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# define UxGCR_CPHA_SECOND_EDGE (1 << 6)
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# define UxGCR_ORDER_LSB (0 << 5)
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# define UxGCR_ORDER_MSB (1 << 5)
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# define UxGCR_BAUD_E_MASK (0x1f)
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# define UxGCR_BAUD_E_SHIFT 0
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sfr at 0xc1 U0DBUF;
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sfr at 0xf9 U1DBUF;
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sfr at 0xc2 U0BAUD;
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sfr at 0xfa U1BAUD;
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#define MOSI P1_5
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#define MISO P1_4
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#define SCK P1_3
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#define CS P1_2
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#define DEBUG P1_1
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#define BITBANG 0
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#define USART 1
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#define nop() _asm nop _endasm;
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void
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delay (unsigned char n)
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{
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unsigned char i = 0;
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unsigned char j = 0;
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while (--n != 0)
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while (--i != 0)
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while (--j != 0)
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nop();
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}
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#if BITBANG
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/*
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* This version directly manipulates the GPIOs to synthesize SPI
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*/
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void
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bitbang_cs(uint8_t b)
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{
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SCK = 0;
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CS = b;
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delay(1);
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}
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void
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bitbang_out_bit(uint8_t b)
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{
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MOSI = b;
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delay(1);
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SCK = 1;
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delay(1);
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SCK = 0;
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}
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void
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bitbang_out_byte(uint8_t byte)
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{
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uint8_t s;
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for (s = 0; s < 8; s++) {
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uint8_t b = (byte & 0x80) ? 1 : 0;
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bitbang_out_bit(b);
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byte <<= 1;
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}
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}
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uint8_t
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bitbang_in_bit(void)
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{
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uint8_t b;
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delay(1);
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SCK = 1;
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delay(1);
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b = MISO;
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SCK = 0;
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return b;
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}
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uint8_t
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bitbang_in_byte(void)
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{
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uint8_t byte = 0;
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uint8_t s;
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uint8_t b;
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for (s = 0; s < 8; s++) {
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b = bitbang_in_bit();
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byte = byte << 1;
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byte |= b;
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}
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return byte;
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}
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void
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bit_bang_init(void)
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{
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CS = 1;
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SCK = 0;
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P1DIR = ((1 << 5) |
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(0 << 4) |
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(1 << 3) |
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(1 << 2) |
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(1 << 1));
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}
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#define spi_init() bitbang_init()
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#define spi_out_byte(b) bitbang_out_byte(b)
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#define spi_in_byte() bitbang_in_byte()
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#define spi_cs(b) bitbang_cs(b)
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#endif
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#if USART
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/*
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* This version uses the USART in SPI mode
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*/
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void
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usart_init(void)
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{
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/*
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* Configure our chip select line
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*/
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CS = 1;
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P1DIR |= (1 << 2);
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/*
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* Configure the peripheral pin choices
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* for both of the serial ports
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*
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* Note that telemetrum will use U1CFG_ALT_2
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* but that overlaps with SPI ALT_2, so until
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* we can test that this works, we'll set this
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* to ALT_1
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*/
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PERCFG = (PERCFG_U1CFG_ALT_1 |
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PERCFG_U0CFG_ALT_2);
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/*
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* Make the SPI pins controlled by the SPI
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* hardware
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*/
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P1SEL |= ((1 << 5) | (1 << 4) | (1 << 3));
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/*
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* SPI in master mode
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*/
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U0CSR = (UxCSR_MODE_SPI |
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UxCSR_MASTER);
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/*
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* The cc1111 is limited to a 24/8 MHz SPI clock,
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* while the 25LC1024 is limited to 20MHz. So,
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* use the 3MHz clock (BAUD_E 17, BAUD_M 0)
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*/
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U0BAUD = 0;
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U0GCR = (UxGCR_CPOL_NEGATIVE |
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UxGCR_CPHA_FIRST_EDGE |
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UxGCR_ORDER_MSB |
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(17 << UxGCR_BAUD_E_SHIFT));
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}
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void
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usart_cs(uint8_t b)
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{
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CS = b;
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}
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uint8_t
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usart_in_out(uint8_t byte)
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{
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U0DBUF = byte;
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while ((U0CSR & UxCSR_TX_BYTE) == 0)
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;
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U0CSR &= ~UxCSR_TX_BYTE;
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return U0DBUF;
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}
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void
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usart_out_byte(uint8_t byte)
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{
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(void) usart_in_out(byte);
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}
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uint8_t
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usart_in_byte(void)
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{
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return usart_in_out(0xff);
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}
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#define spi_init() usart_init()
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#define spi_out_byte(b) usart_out_byte(b)
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#define spi_in_byte() usart_in_byte()
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#define spi_cs(b) usart_cs(b)
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#endif
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uint8_t
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rdsr(void)
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{
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uint8_t status;
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spi_cs(0);
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spi_out_byte(0x05);
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status = spi_in_byte();
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spi_cs(1);
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return status;
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}
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void
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wrsr(uint8_t status)
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{
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spi_cs(0);
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spi_out_byte(0x01);
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spi_out_byte(status);
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spi_cs(1);
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}
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void
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wren(void)
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{
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spi_cs(0);
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spi_out_byte(0x06);
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spi_cs(1);
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}
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void
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write(uint32_t addr, uint8_t *bytes, uint16_t len)
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{
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wren();
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spi_cs(0);
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spi_out_byte(0x02);
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spi_out_byte(addr >> 16);
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spi_out_byte(addr >> 8);
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spi_out_byte(addr);
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while (len-- > 0)
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spi_out_byte(*bytes++);
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spi_cs(1);
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for (;;) {
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uint8_t status = rdsr();
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if ((status & (1 << 0)) == 0)
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break;
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}
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}
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void
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read(uint32_t addr, uint8_t *bytes, uint16_t len)
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{
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spi_cs(0);
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spi_out_byte(0x03);
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spi_out_byte(addr >> 16);
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spi_out_byte(addr >> 8);
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spi_out_byte(addr);
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while (len-- > 0)
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*bytes++ = spi_in_byte();
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spi_cs(1);
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}
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void
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debug_byte(uint8_t byte)
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{
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uint8_t s;
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for (s = 0; s < 8; s++) {
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DEBUG = byte & 1;
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delay(5);
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byte >>= 1;
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}
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}
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#define STRING "\360\252"
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#define LENGTH 2
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main ()
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{
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uint8_t status;
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uint8_t buf[LENGTH];
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int i;
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P1DIR |= 2;
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CLKCON = 0;
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while (!(SLEEP & SLEEP_XOSC_STB))
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;
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spi_init();
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status = rdsr();
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/*
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* Turn off both block-protect bits
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*/
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status &= ~((1 << 3) | (1 << 2));
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/*
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* Turn off write protect enable
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*/
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status &= ~(1 << 7);
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wrsr(status);
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write(0x0, STRING, LENGTH);
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for (;;) {
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read(0x0, buf, LENGTH);
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for (i = 0; i < LENGTH; i++)
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debug_byte(buf[i]);
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}
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}
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