362 lines
8.3 KiB
C
362 lines
8.3 KiB
C
/*
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* Copyright © 2008 Keith Packard <keithp@keithp.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*/
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#include <stdint.h>
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/*
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* Test DMA
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*/
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sfr at 0x80 P0;
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sfr at 0x90 P1;
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sfr at 0xA0 P2;
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sfr at 0xC6 CLKCON;
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sfr at 0xbe SLEEP;
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# define SLEEP_USB_EN (1 << 7)
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# define SLEEP_XOSC_STB (1 << 6)
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sfr at 0xF1 PERCFG;
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#define PERCFG_T1CFG_ALT_1 (0 << 6)
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#define PERCFG_T1CFG_ALT_2 (1 << 6)
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#define PERCFG_T3CFG_ALT_1 (0 << 5)
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#define PERCFG_T3CFG_ALT_2 (1 << 5)
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#define PERCFG_T4CFG_ALT_1 (0 << 4)
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#define PERCFG_T4CFG_ALT_2 (1 << 4)
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#define PERCFG_U1CFG_ALT_1 (0 << 1)
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#define PERCFG_U1CFG_ALT_2 (1 << 1)
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#define PERCFG_U0CFG_ALT_1 (0 << 0)
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#define PERCFG_U0CFG_ALT_2 (1 << 0)
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sfr at 0xF2 ADCCFG;
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sfr at 0xF3 P0SEL;
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sfr at 0xF4 P1SEL;
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sfr at 0xF5 P2SEL;
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sfr at 0xFD P0DIR;
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sfr at 0xFE P1DIR;
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sfr at 0xFF P2DIR;
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sfr at 0x8F P0INP;
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sfr at 0xF6 P1INP;
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sfr at 0xF7 P2INP;
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sfr at 0x89 P0IFG;
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sfr at 0x8A P1IFG;
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sfr at 0x8B P2IFG;
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sbit at 0x90 P1_0;
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sbit at 0x91 P1_1;
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sbit at 0x92 P1_2;
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sbit at 0x93 P1_3;
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sbit at 0x94 P1_4;
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sbit at 0x95 P1_5;
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sbit at 0x96 P1_6;
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sbit at 0x97 P1_7;
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/*
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* UART registers
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*/
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sfr at 0x86 U0CSR;
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sfr at 0xF8 U1CSR;
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/*
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* IRCON2
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*/
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sfr at 0xE8 IRCON2; /* CPU Interrupt Flag 5 */
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sbit at 0xE8 USBIF; /* USB interrupt flag (shared with Port2) */
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sbit at 0xE8 P2IF; /* Port2 interrupt flag (shared with USB) */
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sbit at 0xE9 UTX0IF; /* USART0 TX interrupt flag */
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sbit at 0xEA UTX1IF; /* USART1 TX interrupt flag (shared with I2S TX) */
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sbit at 0xEA I2STXIF; /* I2S TX interrupt flag (shared with USART1 TX) */
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sbit at 0xEB P1IF; /* Port1 interrupt flag */
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sbit at 0xEC WDTIF; /* Watchdog timer interrupt flag */
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# define UxCSR_MODE_UART (1 << 7)
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# define UxCSR_MODE_SPI (0 << 7)
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# define UxCSR_RE (1 << 6)
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# define UxCSR_SLAVE (1 << 5)
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# define UxCSR_MASTER (0 << 5)
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# define UxCSR_FE (1 << 4)
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# define UxCSR_ERR (1 << 3)
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# define UxCSR_RX_BYTE (1 << 2)
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# define UxCSR_TX_BYTE (1 << 1)
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# define UxCSR_ACTIVE (1 << 0)
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sfr at 0xc4 U0UCR;
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sfr at 0xfb U1UCR;
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# define UxUCR_FLUSH (1 << 7)
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# define UxUCR_FLOW_DISABLE (0 << 6)
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# define UxUCR_FLOW_ENABLE (1 << 6)
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# define UxUCR_D9_EVEN_PARITY (0 << 5)
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# define UxUCR_D9_ODD_PARITY (1 << 5)
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# define UxUCR_BIT9_8_BITS (0 << 4)
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# define UxUCR_BIT9_9_BITS (1 << 4)
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# define UxUCR_PARITY_DISABLE (0 << 3)
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# define UxUCR_PARITY_ENABLE (1 << 3)
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# define UxUCR_SPB_1_STOP_BIT (0 << 2)
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# define UxUCR_SPB_2_STOP_BITS (1 << 2)
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# define UxUCR_STOP_LOW (0 << 1)
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# define UxUCR_STOP_HIGH (1 << 1)
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# define UxUCR_START_LOW (0 << 0)
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# define UxUCR_START_HIGH (1 << 0)
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sfr at 0xc5 U0GCR;
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sfr at 0xfc U1GCR;
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# define UxGCR_CPOL_NEGATIVE (0 << 7)
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# define UxGCR_CPOL_POSITIVE (1 << 7)
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# define UxGCR_CPHA_FIRST_EDGE (0 << 6)
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# define UxGCR_CPHA_SECOND_EDGE (1 << 6)
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# define UxGCR_ORDER_LSB (0 << 5)
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# define UxGCR_ORDER_MSB (1 << 5)
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# define UxGCR_BAUD_E_MASK (0x1f)
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# define UxGCR_BAUD_E_SHIFT 0
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sfr at 0xc1 U0DBUF;
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sfr at 0xf9 U1DBUF;
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sfr at 0xc2 U0BAUD;
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sfr at 0xfa U1BAUD;
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#define DEBUG P1_1
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# define DMA_LEN_HIGH_VLEN_MASK (7 << 5)
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# define DMA_LEN_HIGH_VLEN_LEN (0 << 5)
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# define DMA_LEN_HIGH_VLEN_PLUS_1 (1 << 5)
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# define DMA_LEN_HIGH_VLEN (2 << 5)
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# define DMA_LEN_HIGH_VLEN_PLUS_2 (3 << 5)
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# define DMA_LEN_HIGH_VLEN_PLUS_3 (4 << 5)
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# define DMA_LEN_HIGH_MASK (0x1f)
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# define DMA_CFG0_WORDSIZE_8 (0 << 7)
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# define DMA_CFG0_WORDSIZE_16 (1 << 7)
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# define DMA_CFG0_TMODE_MASK (3 << 5)
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# define DMA_CFG0_TMODE_SINGLE (0 << 5)
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# define DMA_CFG0_TMODE_BLOCK (1 << 5)
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# define DMA_CFG0_TMODE_REPEATED_SINGLE (2 << 5)
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# define DMA_CFG0_TMODE_REPEATED_BLOCK (3 << 5)
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/*
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* DMA triggers
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*/
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# define DMA_CFG0_TRIGGER_NONE 0
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# define DMA_CFG0_TRIGGER_PREV 1
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# define DMA_CFG0_TRIGGER_T1_CH0 2
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# define DMA_CFG0_TRIGGER_T1_CH1 3
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# define DMA_CFG0_TRIGGER_T1_CH2 4
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# define DMA_CFG0_TRIGGER_T2_OVFL 6
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# define DMA_CFG0_TRIGGER_T3_CH0 7
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# define DMA_CFG0_TRIGGER_T3_CH1 8
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# define DMA_CFG0_TRIGGER_T4_CH0 9
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# define DMA_CFG0_TRIGGER_T4_CH1 10
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# define DMA_CFG0_TRIGGER_IOC_0 12
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# define DMA_CFG0_TRIGGER_IOC_1 13
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# define DMA_CFG0_TRIGGER_URX0 14
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# define DMA_CFG0_TRIGGER_UTX0 15
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# define DMA_CFG0_TRIGGER_URX1 16
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# define DMA_CFG0_TRIGGER_UTX1 17
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# define DMA_CFG0_TRIGGER_FLASH 18
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# define DMA_CFG0_TRIGGER_RADIO 19
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# define DMA_CFG0_TRIGGER_ADC_CHALL 20
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# define DMA_CFG0_TRIGGER_ADC_CH0 21
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# define DMA_CFG0_TRIGGER_ADC_CH1 22
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# define DMA_CFG0_TRIGGER_ADC_CH2 23
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# define DMA_CFG0_TRIGGER_ADC_CH3 24
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# define DMA_CFG0_TRIGGER_ADC_CH4 25
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# define DMA_CFG0_TRIGGER_ADC_CH5 26
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# define DMA_CFG0_TRIGGER_ADC_CH6 27
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# define DMA_CFG0_TRIGGER_I2SRX 27
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# define DMA_CFG0_TRIGGER_ADC_CH7 28
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# define DMA_CFG0_TRIGGER_I2STX 28
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# define DMA_CFG0_TRIGGER_ENC_DW 29
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# define DMA_CFG0_TRIGGER_DNC_UP 30
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# define DMA_CFG1_SRCINC_MASK (3 << 6)
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# define DMA_CFG1_SRCINC_0 (0 << 6)
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# define DMA_CFG1_SRCINC_1 (1 << 6)
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# define DMA_CFG1_SRCINC_2 (2 << 6)
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# define DMA_CFG1_SRCINC_MINUS_1 (3 << 6)
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# define DMA_CFG1_DESTINC_MASK (3 << 4)
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# define DMA_CFG1_DESTINC_0 (0 << 4)
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# define DMA_CFG1_DESTINC_1 (1 << 4)
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# define DMA_CFG1_DESTINC_2 (2 << 4)
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# define DMA_CFG1_DESTINC_MINUS_1 (3 << 4)
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# define DMA_CFG1_IRQMASK (1 << 3)
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# define DMA_CFG1_M8 (1 << 2)
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# define DMA_CFG1_PRIORITY_MASK (3 << 0)
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# define DMA_CFG1_PRIORITY_LOW (0 << 0)
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# define DMA_CFG1_PRIORITY_NORMAL (1 << 0)
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# define DMA_CFG1_PRIORITY_HIGH (2 << 0)
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/*
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* DMAARM - DMA Channel Arm
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*/
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sfr at 0xD6 DMAARM;
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# define DMAARM_ABORT (1 << 7)
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# define DMAARM_DMAARM4 (1 << 4)
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# define DMAARM_DMAARM3 (1 << 3)
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# define DMAARM_DMAARM2 (1 << 2)
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# define DMAARM_DMAARM1 (1 << 1)
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# define DMAARM_DMAARM0 (1 << 0)
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/*
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* DMAREQ - DMA Channel Start Request and Status
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*/
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sfr at 0xD7 DMAREQ;
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# define DMAREQ_DMAREQ4 (1 << 4)
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# define DMAREQ_DMAREQ3 (1 << 3)
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# define DMAREQ_DMAREQ2 (1 << 2)
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# define DMAREQ_DMAREQ1 (1 << 1)
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# define DMAREQ_DMAREQ0 (1 << 0)
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/*
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* DMA configuration 0 address
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*/
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sfr at 0xD5 DMA0CFGH;
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sfr at 0xD4 DMA0CFGL;
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/*
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* DMA configuration 1-4 address
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*/
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sfr at 0xD3 DMA1CFGH;
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sfr at 0xD2 DMA1CFGL;
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/*
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* DMAIRQ - DMA Interrupt Flag
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*/
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sfr at 0xD1 DMAIRQ;
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# define DMAIRQ_DMAIF4 (1 << 4)
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# define DMAIRQ_DMAIF3 (1 << 3)
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# define DMAIRQ_DMAIF2 (1 << 2)
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# define DMAIRQ_DMAIF1 (1 << 1)
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# define DMAIRQ_DMAIF0 (1 << 0)
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struct cc_dma_channel {
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uint8_t src_high;
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uint8_t src_low;
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uint8_t dst_high;
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uint8_t dst_low;
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uint8_t len_high;
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uint8_t len_low;
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uint8_t cfg0;
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uint8_t cfg1;
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};
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#define nop() _asm nop _endasm;
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void
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delay (unsigned char n)
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{
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unsigned char i = 0;
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unsigned char j = 0;
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n++;
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while (--n != 0)
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while (--i != 0)
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while (--j != 0)
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nop();
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}
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void
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debug_byte(uint8_t byte)
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{
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uint8_t s;
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for (s = 0; s < 8; s++) {
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DEBUG = byte & 1;
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delay(5);
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byte >>= 1;
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}
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}
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struct cc_dma_channel __xdata config;
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#define DMA_LEN 8
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uint8_t __xdata dma_input[DMA_LEN];
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uint8_t __xdata dma_output[DMA_LEN];
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#define ADDRH(a) (((uint16_t) (a)) >> 8)
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#define ADDRL(a) (((uint16_t) (a)))
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void
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dma_init(void)
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{
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int i;
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config.cfg0 = (DMA_CFG0_WORDSIZE_8 |
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DMA_CFG0_TMODE_BLOCK |
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DMA_CFG0_TRIGGER_NONE);
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config.cfg1 = (DMA_CFG1_SRCINC_1 |
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DMA_CFG1_DESTINC_1 |
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DMA_CFG1_PRIORITY_NORMAL);
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config.src_high = ADDRH(dma_input);
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config.src_low = ADDRL(dma_input);
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config.dst_high = ADDRH(dma_output);
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config.dst_low = ADDRL(dma_output);
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config.len_high = 0;
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config.len_low = DMA_LEN;
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DMA0CFGH = ADDRH(&config);
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DMA0CFGL = ADDRL(&config);
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for (i = 0; i < DMA_LEN; i++)
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dma_input[i] = i + 1;
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}
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void
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dma_run(void)
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{
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DMAREQ |= 1;
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DMAARM |= 1;
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while (DMAARM & 1)
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;
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}
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main ()
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{
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int i;
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P1DIR |= 2;
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CLKCON = 0;
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while (!(SLEEP & SLEEP_XOSC_STB))
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;
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dma_init();
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dma_run();
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for (;;) {
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for (i = 0; i < DMA_LEN; i++)
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debug_byte(dma_output[i]);
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}
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}
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