ALPAKA/CAN-Demo
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CAN-Demo/Debug/can-tests.list
@CarlWachter 18bcba3706 Initial WIP build
2023-10-25 16:19:32 +02:00

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261 KiB
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can-tests.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00002a40 08000188 08000188 00010188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000d4 08002bc8 08002bc8 00012bc8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002c9c 08002c9c 0002000c 2**0
CONTENTS
4 .ARM 00000008 08002c9c 08002c9c 00012c9c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08002ca4 08002ca4 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002ca4 08002ca4 00012ca4 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08002ca8 08002ca8 00012ca8 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08002cac 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .ccmram 00000000 10000000 10000000 0002000c 2**0
CONTENTS
10 .bss 0000008c 2000000c 2000000c 0002000c 2**2
ALLOC
11 ._user_heap_stack 00000600 20000098 20000098 0002000c 2**0
ALLOC
12 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
13 .comment 00000043 00000000 00000000 0002003c 2**0
CONTENTS, READONLY
14 .debug_info 0000bed9 00000000 00000000 0002007f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_abbrev 0000205f 00000000 00000000 0002bf58 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_aranges 000008b8 00000000 00000000 0002dfb8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_rnglists 00000695 00000000 00000000 0002e870 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_macro 00022499 00000000 00000000 0002ef05 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_line 0000b635 00000000 00000000 0005139e 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_str 000c7dc8 00000000 00000000 0005c9d3 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_frame 00002290 00000000 00000000 0012479c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
22 .debug_line_str 00000065 00000000 00000000 00126a2c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 2000000c .word 0x2000000c
80001a4: 00000000 .word 0x00000000
80001a8: 08002bb0 .word 0x08002bb0
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000010 .word 0x20000010
80001c4: 08002bb0 .word 0x08002bb0
080001c8 <__aeabi_uldivmod>:
80001c8: b953 cbnz r3, 80001e0 <__aeabi_uldivmod+0x18>
80001ca: b94a cbnz r2, 80001e0 <__aeabi_uldivmod+0x18>
80001cc: 2900 cmp r1, #0
80001ce: bf08 it eq
80001d0: 2800 cmpeq r0, #0
80001d2: bf1c itt ne
80001d4: f04f 31ff movne.w r1, #4294967295
80001d8: f04f 30ff movne.w r0, #4294967295
80001dc: f000 b970 b.w 80004c0 <__aeabi_idiv0>
80001e0: f1ad 0c08 sub.w ip, sp, #8
80001e4: e96d ce04 strd ip, lr, [sp, #-16]!
80001e8: f000 f806 bl 80001f8 <__udivmoddi4>
80001ec: f8dd e004 ldr.w lr, [sp, #4]
80001f0: e9dd 2302 ldrd r2, r3, [sp, #8]
80001f4: b004 add sp, #16
80001f6: 4770 bx lr
080001f8 <__udivmoddi4>:
80001f8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
80001fc: 9e08 ldr r6, [sp, #32]
80001fe: 460d mov r5, r1
8000200: 4604 mov r4, r0
8000202: 460f mov r7, r1
8000204: 2b00 cmp r3, #0
8000206: d14a bne.n 800029e <__udivmoddi4+0xa6>
8000208: 428a cmp r2, r1
800020a: 4694 mov ip, r2
800020c: d965 bls.n 80002da <__udivmoddi4+0xe2>
800020e: fab2 f382 clz r3, r2
8000212: b143 cbz r3, 8000226 <__udivmoddi4+0x2e>
8000214: fa02 fc03 lsl.w ip, r2, r3
8000218: f1c3 0220 rsb r2, r3, #32
800021c: 409f lsls r7, r3
800021e: fa20 f202 lsr.w r2, r0, r2
8000222: 4317 orrs r7, r2
8000224: 409c lsls r4, r3
8000226: ea4f 4e1c mov.w lr, ip, lsr #16
800022a: fa1f f58c uxth.w r5, ip
800022e: fbb7 f1fe udiv r1, r7, lr
8000232: 0c22 lsrs r2, r4, #16
8000234: fb0e 7711 mls r7, lr, r1, r7
8000238: ea42 4207 orr.w r2, r2, r7, lsl #16
800023c: fb01 f005 mul.w r0, r1, r5
8000240: 4290 cmp r0, r2
8000242: d90a bls.n 800025a <__udivmoddi4+0x62>
8000244: eb1c 0202 adds.w r2, ip, r2
8000248: f101 37ff add.w r7, r1, #4294967295
800024c: f080 811c bcs.w 8000488 <__udivmoddi4+0x290>
8000250: 4290 cmp r0, r2
8000252: f240 8119 bls.w 8000488 <__udivmoddi4+0x290>
8000256: 3902 subs r1, #2
8000258: 4462 add r2, ip
800025a: 1a12 subs r2, r2, r0
800025c: b2a4 uxth r4, r4
800025e: fbb2 f0fe udiv r0, r2, lr
8000262: fb0e 2210 mls r2, lr, r0, r2
8000266: ea44 4402 orr.w r4, r4, r2, lsl #16
800026a: fb00 f505 mul.w r5, r0, r5
800026e: 42a5 cmp r5, r4
8000270: d90a bls.n 8000288 <__udivmoddi4+0x90>
8000272: eb1c 0404 adds.w r4, ip, r4
8000276: f100 32ff add.w r2, r0, #4294967295
800027a: f080 8107 bcs.w 800048c <__udivmoddi4+0x294>
800027e: 42a5 cmp r5, r4
8000280: f240 8104 bls.w 800048c <__udivmoddi4+0x294>
8000284: 4464 add r4, ip
8000286: 3802 subs r0, #2
8000288: ea40 4001 orr.w r0, r0, r1, lsl #16
800028c: 1b64 subs r4, r4, r5
800028e: 2100 movs r1, #0
8000290: b11e cbz r6, 800029a <__udivmoddi4+0xa2>
8000292: 40dc lsrs r4, r3
8000294: 2300 movs r3, #0
8000296: e9c6 4300 strd r4, r3, [r6]
800029a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
800029e: 428b cmp r3, r1
80002a0: d908 bls.n 80002b4 <__udivmoddi4+0xbc>
80002a2: 2e00 cmp r6, #0
80002a4: f000 80ed beq.w 8000482 <__udivmoddi4+0x28a>
80002a8: 2100 movs r1, #0
80002aa: e9c6 0500 strd r0, r5, [r6]
80002ae: 4608 mov r0, r1
80002b0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002b4: fab3 f183 clz r1, r3
80002b8: 2900 cmp r1, #0
80002ba: d149 bne.n 8000350 <__udivmoddi4+0x158>
80002bc: 42ab cmp r3, r5
80002be: d302 bcc.n 80002c6 <__udivmoddi4+0xce>
80002c0: 4282 cmp r2, r0
80002c2: f200 80f8 bhi.w 80004b6 <__udivmoddi4+0x2be>
80002c6: 1a84 subs r4, r0, r2
80002c8: eb65 0203 sbc.w r2, r5, r3
80002cc: 2001 movs r0, #1
80002ce: 4617 mov r7, r2
80002d0: 2e00 cmp r6, #0
80002d2: d0e2 beq.n 800029a <__udivmoddi4+0xa2>
80002d4: e9c6 4700 strd r4, r7, [r6]
80002d8: e7df b.n 800029a <__udivmoddi4+0xa2>
80002da: b902 cbnz r2, 80002de <__udivmoddi4+0xe6>
80002dc: deff udf #255 ; 0xff
80002de: fab2 f382 clz r3, r2
80002e2: 2b00 cmp r3, #0
80002e4: f040 8090 bne.w 8000408 <__udivmoddi4+0x210>
80002e8: 1a8a subs r2, r1, r2
80002ea: ea4f 471c mov.w r7, ip, lsr #16
80002ee: fa1f fe8c uxth.w lr, ip
80002f2: 2101 movs r1, #1
80002f4: fbb2 f5f7 udiv r5, r2, r7
80002f8: fb07 2015 mls r0, r7, r5, r2
80002fc: 0c22 lsrs r2, r4, #16
80002fe: ea42 4200 orr.w r2, r2, r0, lsl #16
8000302: fb0e f005 mul.w r0, lr, r5
8000306: 4290 cmp r0, r2
8000308: d908 bls.n 800031c <__udivmoddi4+0x124>
800030a: eb1c 0202 adds.w r2, ip, r2
800030e: f105 38ff add.w r8, r5, #4294967295
8000312: d202 bcs.n 800031a <__udivmoddi4+0x122>
8000314: 4290 cmp r0, r2
8000316: f200 80cb bhi.w 80004b0 <__udivmoddi4+0x2b8>
800031a: 4645 mov r5, r8
800031c: 1a12 subs r2, r2, r0
800031e: b2a4 uxth r4, r4
8000320: fbb2 f0f7 udiv r0, r2, r7
8000324: fb07 2210 mls r2, r7, r0, r2
8000328: ea44 4402 orr.w r4, r4, r2, lsl #16
800032c: fb0e fe00 mul.w lr, lr, r0
8000330: 45a6 cmp lr, r4
8000332: d908 bls.n 8000346 <__udivmoddi4+0x14e>
8000334: eb1c 0404 adds.w r4, ip, r4
8000338: f100 32ff add.w r2, r0, #4294967295
800033c: d202 bcs.n 8000344 <__udivmoddi4+0x14c>
800033e: 45a6 cmp lr, r4
8000340: f200 80bb bhi.w 80004ba <__udivmoddi4+0x2c2>
8000344: 4610 mov r0, r2
8000346: eba4 040e sub.w r4, r4, lr
800034a: ea40 4005 orr.w r0, r0, r5, lsl #16
800034e: e79f b.n 8000290 <__udivmoddi4+0x98>
8000350: f1c1 0720 rsb r7, r1, #32
8000354: 408b lsls r3, r1
8000356: fa22 fc07 lsr.w ip, r2, r7
800035a: ea4c 0c03 orr.w ip, ip, r3
800035e: fa05 f401 lsl.w r4, r5, r1
8000362: fa20 f307 lsr.w r3, r0, r7
8000366: 40fd lsrs r5, r7
8000368: ea4f 491c mov.w r9, ip, lsr #16
800036c: 4323 orrs r3, r4
800036e: fbb5 f8f9 udiv r8, r5, r9
8000372: fa1f fe8c uxth.w lr, ip
8000376: fb09 5518 mls r5, r9, r8, r5
800037a: 0c1c lsrs r4, r3, #16
800037c: ea44 4405 orr.w r4, r4, r5, lsl #16
8000380: fb08 f50e mul.w r5, r8, lr
8000384: 42a5 cmp r5, r4
8000386: fa02 f201 lsl.w r2, r2, r1
800038a: fa00 f001 lsl.w r0, r0, r1
800038e: d90b bls.n 80003a8 <__udivmoddi4+0x1b0>
8000390: eb1c 0404 adds.w r4, ip, r4
8000394: f108 3aff add.w sl, r8, #4294967295
8000398: f080 8088 bcs.w 80004ac <__udivmoddi4+0x2b4>
800039c: 42a5 cmp r5, r4
800039e: f240 8085 bls.w 80004ac <__udivmoddi4+0x2b4>
80003a2: f1a8 0802 sub.w r8, r8, #2
80003a6: 4464 add r4, ip
80003a8: 1b64 subs r4, r4, r5
80003aa: b29d uxth r5, r3
80003ac: fbb4 f3f9 udiv r3, r4, r9
80003b0: fb09 4413 mls r4, r9, r3, r4
80003b4: ea45 4404 orr.w r4, r5, r4, lsl #16
80003b8: fb03 fe0e mul.w lr, r3, lr
80003bc: 45a6 cmp lr, r4
80003be: d908 bls.n 80003d2 <__udivmoddi4+0x1da>
80003c0: eb1c 0404 adds.w r4, ip, r4
80003c4: f103 35ff add.w r5, r3, #4294967295
80003c8: d26c bcs.n 80004a4 <__udivmoddi4+0x2ac>
80003ca: 45a6 cmp lr, r4
80003cc: d96a bls.n 80004a4 <__udivmoddi4+0x2ac>
80003ce: 3b02 subs r3, #2
80003d0: 4464 add r4, ip
80003d2: ea43 4308 orr.w r3, r3, r8, lsl #16
80003d6: fba3 9502 umull r9, r5, r3, r2
80003da: eba4 040e sub.w r4, r4, lr
80003de: 42ac cmp r4, r5
80003e0: 46c8 mov r8, r9
80003e2: 46ae mov lr, r5
80003e4: d356 bcc.n 8000494 <__udivmoddi4+0x29c>
80003e6: d053 beq.n 8000490 <__udivmoddi4+0x298>
80003e8: b156 cbz r6, 8000400 <__udivmoddi4+0x208>
80003ea: ebb0 0208 subs.w r2, r0, r8
80003ee: eb64 040e sbc.w r4, r4, lr
80003f2: fa04 f707 lsl.w r7, r4, r7
80003f6: 40ca lsrs r2, r1
80003f8: 40cc lsrs r4, r1
80003fa: 4317 orrs r7, r2
80003fc: e9c6 7400 strd r7, r4, [r6]
8000400: 4618 mov r0, r3
8000402: 2100 movs r1, #0
8000404: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000408: f1c3 0120 rsb r1, r3, #32
800040c: fa02 fc03 lsl.w ip, r2, r3
8000410: fa20 f201 lsr.w r2, r0, r1
8000414: fa25 f101 lsr.w r1, r5, r1
8000418: 409d lsls r5, r3
800041a: 432a orrs r2, r5
800041c: ea4f 471c mov.w r7, ip, lsr #16
8000420: fa1f fe8c uxth.w lr, ip
8000424: fbb1 f0f7 udiv r0, r1, r7
8000428: fb07 1510 mls r5, r7, r0, r1
800042c: 0c11 lsrs r1, r2, #16
800042e: ea41 4105 orr.w r1, r1, r5, lsl #16
8000432: fb00 f50e mul.w r5, r0, lr
8000436: 428d cmp r5, r1
8000438: fa04 f403 lsl.w r4, r4, r3
800043c: d908 bls.n 8000450 <__udivmoddi4+0x258>
800043e: eb1c 0101 adds.w r1, ip, r1
8000442: f100 38ff add.w r8, r0, #4294967295
8000446: d22f bcs.n 80004a8 <__udivmoddi4+0x2b0>
8000448: 428d cmp r5, r1
800044a: d92d bls.n 80004a8 <__udivmoddi4+0x2b0>
800044c: 3802 subs r0, #2
800044e: 4461 add r1, ip
8000450: 1b49 subs r1, r1, r5
8000452: b292 uxth r2, r2
8000454: fbb1 f5f7 udiv r5, r1, r7
8000458: fb07 1115 mls r1, r7, r5, r1
800045c: ea42 4201 orr.w r2, r2, r1, lsl #16
8000460: fb05 f10e mul.w r1, r5, lr
8000464: 4291 cmp r1, r2
8000466: d908 bls.n 800047a <__udivmoddi4+0x282>
8000468: eb1c 0202 adds.w r2, ip, r2
800046c: f105 38ff add.w r8, r5, #4294967295
8000470: d216 bcs.n 80004a0 <__udivmoddi4+0x2a8>
8000472: 4291 cmp r1, r2
8000474: d914 bls.n 80004a0 <__udivmoddi4+0x2a8>
8000476: 3d02 subs r5, #2
8000478: 4462 add r2, ip
800047a: 1a52 subs r2, r2, r1
800047c: ea45 4100 orr.w r1, r5, r0, lsl #16
8000480: e738 b.n 80002f4 <__udivmoddi4+0xfc>
8000482: 4631 mov r1, r6
8000484: 4630 mov r0, r6
8000486: e708 b.n 800029a <__udivmoddi4+0xa2>
8000488: 4639 mov r1, r7
800048a: e6e6 b.n 800025a <__udivmoddi4+0x62>
800048c: 4610 mov r0, r2
800048e: e6fb b.n 8000288 <__udivmoddi4+0x90>
8000490: 4548 cmp r0, r9
8000492: d2a9 bcs.n 80003e8 <__udivmoddi4+0x1f0>
8000494: ebb9 0802 subs.w r8, r9, r2
8000498: eb65 0e0c sbc.w lr, r5, ip
800049c: 3b01 subs r3, #1
800049e: e7a3 b.n 80003e8 <__udivmoddi4+0x1f0>
80004a0: 4645 mov r5, r8
80004a2: e7ea b.n 800047a <__udivmoddi4+0x282>
80004a4: 462b mov r3, r5
80004a6: e794 b.n 80003d2 <__udivmoddi4+0x1da>
80004a8: 4640 mov r0, r8
80004aa: e7d1 b.n 8000450 <__udivmoddi4+0x258>
80004ac: 46d0 mov r8, sl
80004ae: e77b b.n 80003a8 <__udivmoddi4+0x1b0>
80004b0: 3d02 subs r5, #2
80004b2: 4462 add r2, ip
80004b4: e732 b.n 800031c <__udivmoddi4+0x124>
80004b6: 4608 mov r0, r1
80004b8: e70a b.n 80002d0 <__udivmoddi4+0xd8>
80004ba: 4464 add r4, ip
80004bc: 3802 subs r0, #2
80004be: e742 b.n 8000346 <__udivmoddi4+0x14e>
080004c0 <__aeabi_idiv0>:
80004c0: 4770 bx lr
80004c2: bf00 nop
080004c4 <testCan>:
#include <sta/devices/stm32/can.hpp>
//extern STM32CanController(CAN_HandleTypeDef * handle);
extern "C" void testCan(CAN_HandleTypeDef * handle){
80004c4: b580 push {r7, lr}
80004c6: f5ad 7d16 sub.w sp, sp, #600 ; 0x258
80004ca: af00 add r7, sp, #0
80004cc: f507 7316 add.w r3, r7, #600 ; 0x258
80004d0: f5a3 7315 sub.w r3, r3, #596 ; 0x254
80004d4: 6018 str r0, [r3, #0]
sta::STM32CanController canController(handle);
80004d6: f507 7316 add.w r3, r7, #600 ; 0x258
80004da: f5a3 7315 sub.w r3, r3, #596 ; 0x254
80004de: f107 0220 add.w r2, r7, #32
80004e2: 6819 ldr r1, [r3, #0]
80004e4: 4610 mov r0, r2
80004e6: f002 f939 bl 800275c <_ZN3sta18STM32CanControllerC1EP19__CAN_HandleTypeDef>
canController.start();
80004ea: f107 0320 add.w r3, r7, #32
80004ee: 4618 mov r0, r3
80004f0: f002 f94e bl 8002790 <_ZN3sta18STM32CanController5startEv>
// Create a CanTxHeader for your message
sta::CanTxHeader txHeader;
txHeader.id.format = sta::CanIdFormat::EXT; // Set to EXT for extended ID
80004f4: f507 7316 add.w r3, r7, #600 ; 0x258
80004f8: f5a3 7312 sub.w r3, r3, #584 ; 0x248
80004fc: 2201 movs r2, #1
80004fe: 701a strb r2, [r3, #0]
txHeader.id.eid = 0xCAFE; // Set the standard ID or extended ID
8000500: f507 7316 add.w r3, r7, #600 ; 0x258
8000504: f5a3 7312 sub.w r3, r3, #584 ; 0x248
8000508: f64c 22fe movw r2, #51966 ; 0xcafe
800050c: 609a str r2, [r3, #8]
txHeader.payloadLength = 8; // Set the payload length (max 8 bytes)
800050e: f507 7316 add.w r3, r7, #600 ; 0x258
8000512: f5a3 7312 sub.w r3, r3, #584 ; 0x248
8000516: 2208 movs r2, #8
8000518: 731a strb r2, [r3, #12]
// Create your message payload
uint8_t payload[8] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
800051a: f507 7316 add.w r3, r7, #600 ; 0x258
800051e: f5a3 7314 sub.w r3, r3, #592 ; 0x250
8000522: 4a07 ldr r2, [pc, #28] ; (8000540 <testCan+0x7c>)
8000524: e892 0003 ldmia.w r2, {r0, r1}
8000528: e883 0003 stmia.w r3, {r0, r1}
// Send the CAN message
while (true){
canController.sendFrame(txHeader, payload);
800052c: f107 0208 add.w r2, r7, #8
8000530: f107 0110 add.w r1, r7, #16
8000534: f107 0320 add.w r3, r7, #32
8000538: 4618 mov r0, r3
800053a: f002 f937 bl 80027ac <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh>
800053e: e7f5 b.n 800052c <testCan+0x68>
8000540: 08002bc8 .word 0x08002bc8
08000544 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000544: b580 push {r7, lr}
8000546: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8000548: f000 fa5c bl 8000a04 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800054c: f000 f814 bl 8000578 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000550: f000 f8ce bl 80006f0 <MX_GPIO_Init>
MX_CAN1_Init();
8000554: f000 f86e bl 8000634 <MX_CAN1_Init>
MX_UART4_Init();
8000558: f000 f8a0 bl 800069c <MX_UART4_Init>
/* USER CODE BEGIN 2 */
testCan(&hcan1);
800055c: 4804 ldr r0, [pc, #16] ; (8000570 <main+0x2c>)
800055e: f7ff ffb1 bl 80004c4 <testCan>
HAL_GPIO_TogglePin(GPIOB,GPIO_PIN_12);
8000562: f44f 5180 mov.w r1, #4096 ; 0x1000
8000566: 4803 ldr r0, [pc, #12] ; (8000574 <main+0x30>)
8000568: f001 f98f bl 800188a <HAL_GPIO_TogglePin>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
800056c: e7fe b.n 800056c <main+0x28>
800056e: bf00 nop
8000570: 20000028 .word 0x20000028
8000574: 40020400 .word 0x40020400
08000578 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000578: b580 push {r7, lr}
800057a: b094 sub sp, #80 ; 0x50
800057c: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800057e: f107 0320 add.w r3, r7, #32
8000582: 2230 movs r2, #48 ; 0x30
8000584: 2100 movs r1, #0
8000586: 4618 mov r0, r3
8000588: f002 fae5 bl 8002b56 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800058c: f107 030c add.w r3, r7, #12
8000590: 2200 movs r2, #0
8000592: 601a str r2, [r3, #0]
8000594: 605a str r2, [r3, #4]
8000596: 609a str r2, [r3, #8]
8000598: 60da str r2, [r3, #12]
800059a: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
800059c: 2300 movs r3, #0
800059e: 60bb str r3, [r7, #8]
80005a0: 4b22 ldr r3, [pc, #136] ; (800062c <SystemClock_Config+0xb4>)
80005a2: 6c1b ldr r3, [r3, #64] ; 0x40
80005a4: 4a21 ldr r2, [pc, #132] ; (800062c <SystemClock_Config+0xb4>)
80005a6: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80005aa: 6413 str r3, [r2, #64] ; 0x40
80005ac: 4b1f ldr r3, [pc, #124] ; (800062c <SystemClock_Config+0xb4>)
80005ae: 6c1b ldr r3, [r3, #64] ; 0x40
80005b0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80005b4: 60bb str r3, [r7, #8]
80005b6: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
80005b8: 2300 movs r3, #0
80005ba: 607b str r3, [r7, #4]
80005bc: 4b1c ldr r3, [pc, #112] ; (8000630 <SystemClock_Config+0xb8>)
80005be: 681b ldr r3, [r3, #0]
80005c0: 4a1b ldr r2, [pc, #108] ; (8000630 <SystemClock_Config+0xb8>)
80005c2: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80005c6: 6013 str r3, [r2, #0]
80005c8: 4b19 ldr r3, [pc, #100] ; (8000630 <SystemClock_Config+0xb8>)
80005ca: 681b ldr r3, [r3, #0]
80005cc: f403 4380 and.w r3, r3, #16384 ; 0x4000
80005d0: 607b str r3, [r7, #4]
80005d2: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80005d4: 2302 movs r3, #2
80005d6: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80005d8: 2301 movs r3, #1
80005da: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80005dc: 2310 movs r3, #16
80005de: 633b str r3, [r7, #48] ; 0x30
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
80005e0: 2300 movs r3, #0
80005e2: 63bb str r3, [r7, #56] ; 0x38
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80005e4: f107 0320 add.w r3, r7, #32
80005e8: 4618 mov r0, r3
80005ea: f001 f969 bl 80018c0 <HAL_RCC_OscConfig>
80005ee: 4603 mov r3, r0
80005f0: 2b00 cmp r3, #0
80005f2: d001 beq.n 80005f8 <SystemClock_Config+0x80>
{
Error_Handler();
80005f4: f000 f8e2 bl 80007bc <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80005f8: 230f movs r3, #15
80005fa: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
80005fc: 2300 movs r3, #0
80005fe: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000600: 2300 movs r3, #0
8000602: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8000604: 2300 movs r3, #0
8000606: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000608: 2300 movs r3, #0
800060a: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
800060c: f107 030c add.w r3, r7, #12
8000610: 2100 movs r1, #0
8000612: 4618 mov r0, r3
8000614: f001 fbcc bl 8001db0 <HAL_RCC_ClockConfig>
8000618: 4603 mov r3, r0
800061a: 2b00 cmp r3, #0
800061c: d001 beq.n 8000622 <SystemClock_Config+0xaa>
{
Error_Handler();
800061e: f000 f8cd bl 80007bc <Error_Handler>
}
}
8000622: bf00 nop
8000624: 3750 adds r7, #80 ; 0x50
8000626: 46bd mov sp, r7
8000628: bd80 pop {r7, pc}
800062a: bf00 nop
800062c: 40023800 .word 0x40023800
8000630: 40007000 .word 0x40007000
08000634 <MX_CAN1_Init>:
* @brief CAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_CAN1_Init(void)
{
8000634: b580 push {r7, lr}
8000636: af00 add r7, sp, #0
/* USER CODE END CAN1_Init 0 */
/* USER CODE BEGIN CAN1_Init 1 */
/* USER CODE END CAN1_Init 1 */
hcan1.Instance = CAN1;
8000638: 4b16 ldr r3, [pc, #88] ; (8000694 <MX_CAN1_Init+0x60>)
800063a: 4a17 ldr r2, [pc, #92] ; (8000698 <MX_CAN1_Init+0x64>)
800063c: 601a str r2, [r3, #0]
hcan1.Init.Prescaler = 16;
800063e: 4b15 ldr r3, [pc, #84] ; (8000694 <MX_CAN1_Init+0x60>)
8000640: 2210 movs r2, #16
8000642: 605a str r2, [r3, #4]
hcan1.Init.Mode = CAN_MODE_NORMAL;
8000644: 4b13 ldr r3, [pc, #76] ; (8000694 <MX_CAN1_Init+0x60>)
8000646: 2200 movs r2, #0
8000648: 609a str r2, [r3, #8]
hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
800064a: 4b12 ldr r3, [pc, #72] ; (8000694 <MX_CAN1_Init+0x60>)
800064c: 2200 movs r2, #0
800064e: 60da str r2, [r3, #12]
hcan1.Init.TimeSeg1 = CAN_BS1_1TQ;
8000650: 4b10 ldr r3, [pc, #64] ; (8000694 <MX_CAN1_Init+0x60>)
8000652: 2200 movs r2, #0
8000654: 611a str r2, [r3, #16]
hcan1.Init.TimeSeg2 = CAN_BS2_1TQ;
8000656: 4b0f ldr r3, [pc, #60] ; (8000694 <MX_CAN1_Init+0x60>)
8000658: 2200 movs r2, #0
800065a: 615a str r2, [r3, #20]
hcan1.Init.TimeTriggeredMode = DISABLE;
800065c: 4b0d ldr r3, [pc, #52] ; (8000694 <MX_CAN1_Init+0x60>)
800065e: 2200 movs r2, #0
8000660: 761a strb r2, [r3, #24]
hcan1.Init.AutoBusOff = DISABLE;
8000662: 4b0c ldr r3, [pc, #48] ; (8000694 <MX_CAN1_Init+0x60>)
8000664: 2200 movs r2, #0
8000666: 765a strb r2, [r3, #25]
hcan1.Init.AutoWakeUp = DISABLE;
8000668: 4b0a ldr r3, [pc, #40] ; (8000694 <MX_CAN1_Init+0x60>)
800066a: 2200 movs r2, #0
800066c: 769a strb r2, [r3, #26]
hcan1.Init.AutoRetransmission = DISABLE;
800066e: 4b09 ldr r3, [pc, #36] ; (8000694 <MX_CAN1_Init+0x60>)
8000670: 2200 movs r2, #0
8000672: 76da strb r2, [r3, #27]
hcan1.Init.ReceiveFifoLocked = DISABLE;
8000674: 4b07 ldr r3, [pc, #28] ; (8000694 <MX_CAN1_Init+0x60>)
8000676: 2200 movs r2, #0
8000678: 771a strb r2, [r3, #28]
hcan1.Init.TransmitFifoPriority = DISABLE;
800067a: 4b06 ldr r3, [pc, #24] ; (8000694 <MX_CAN1_Init+0x60>)
800067c: 2200 movs r2, #0
800067e: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan1) != HAL_OK)
8000680: 4804 ldr r0, [pc, #16] ; (8000694 <MX_CAN1_Init+0x60>)
8000682: f000 fa31 bl 8000ae8 <HAL_CAN_Init>
8000686: 4603 mov r3, r0
8000688: 2b00 cmp r3, #0
800068a: d001 beq.n 8000690 <MX_CAN1_Init+0x5c>
{
Error_Handler();
800068c: f000 f896 bl 80007bc <Error_Handler>
}
/* USER CODE BEGIN CAN1_Init 2 */
/* USER CODE END CAN1_Init 2 */
}
8000690: bf00 nop
8000692: bd80 pop {r7, pc}
8000694: 20000028 .word 0x20000028
8000698: 40006400 .word 0x40006400
0800069c <MX_UART4_Init>:
* @brief UART4 Initialization Function
* @param None
* @retval None
*/
static void MX_UART4_Init(void)
{
800069c: b580 push {r7, lr}
800069e: af00 add r7, sp, #0
/* USER CODE END UART4_Init 0 */
/* USER CODE BEGIN UART4_Init 1 */
/* USER CODE END UART4_Init 1 */
huart4.Instance = UART4;
80006a0: 4b11 ldr r3, [pc, #68] ; (80006e8 <MX_UART4_Init+0x4c>)
80006a2: 4a12 ldr r2, [pc, #72] ; (80006ec <MX_UART4_Init+0x50>)
80006a4: 601a str r2, [r3, #0]
huart4.Init.BaudRate = 115200;
80006a6: 4b10 ldr r3, [pc, #64] ; (80006e8 <MX_UART4_Init+0x4c>)
80006a8: f44f 32e1 mov.w r2, #115200 ; 0x1c200
80006ac: 605a str r2, [r3, #4]
huart4.Init.WordLength = UART_WORDLENGTH_8B;
80006ae: 4b0e ldr r3, [pc, #56] ; (80006e8 <MX_UART4_Init+0x4c>)
80006b0: 2200 movs r2, #0
80006b2: 609a str r2, [r3, #8]
huart4.Init.StopBits = UART_STOPBITS_1;
80006b4: 4b0c ldr r3, [pc, #48] ; (80006e8 <MX_UART4_Init+0x4c>)
80006b6: 2200 movs r2, #0
80006b8: 60da str r2, [r3, #12]
huart4.Init.Parity = UART_PARITY_NONE;
80006ba: 4b0b ldr r3, [pc, #44] ; (80006e8 <MX_UART4_Init+0x4c>)
80006bc: 2200 movs r2, #0
80006be: 611a str r2, [r3, #16]
huart4.Init.Mode = UART_MODE_TX_RX;
80006c0: 4b09 ldr r3, [pc, #36] ; (80006e8 <MX_UART4_Init+0x4c>)
80006c2: 220c movs r2, #12
80006c4: 615a str r2, [r3, #20]
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80006c6: 4b08 ldr r3, [pc, #32] ; (80006e8 <MX_UART4_Init+0x4c>)
80006c8: 2200 movs r2, #0
80006ca: 619a str r2, [r3, #24]
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
80006cc: 4b06 ldr r3, [pc, #24] ; (80006e8 <MX_UART4_Init+0x4c>)
80006ce: 2200 movs r2, #0
80006d0: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart4) != HAL_OK)
80006d2: 4805 ldr r0, [pc, #20] ; (80006e8 <MX_UART4_Init+0x4c>)
80006d4: f001 fd4c bl 8002170 <HAL_UART_Init>
80006d8: 4603 mov r3, r0
80006da: 2b00 cmp r3, #0
80006dc: d001 beq.n 80006e2 <MX_UART4_Init+0x46>
{
Error_Handler();
80006de: f000 f86d bl 80007bc <Error_Handler>
}
/* USER CODE BEGIN UART4_Init 2 */
/* USER CODE END UART4_Init 2 */
}
80006e2: bf00 nop
80006e4: bd80 pop {r7, pc}
80006e6: bf00 nop
80006e8: 20000050 .word 0x20000050
80006ec: 40004c00 .word 0x40004c00
080006f0 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80006f0: b580 push {r7, lr}
80006f2: b088 sub sp, #32
80006f4: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80006f6: f107 030c add.w r3, r7, #12
80006fa: 2200 movs r2, #0
80006fc: 601a str r2, [r3, #0]
80006fe: 605a str r2, [r3, #4]
8000700: 609a str r2, [r3, #8]
8000702: 60da str r2, [r3, #12]
8000704: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
8000706: 2300 movs r3, #0
8000708: 60bb str r3, [r7, #8]
800070a: 4b29 ldr r3, [pc, #164] ; (80007b0 <MX_GPIO_Init+0xc0>)
800070c: 6b1b ldr r3, [r3, #48] ; 0x30
800070e: 4a28 ldr r2, [pc, #160] ; (80007b0 <MX_GPIO_Init+0xc0>)
8000710: f043 0301 orr.w r3, r3, #1
8000714: 6313 str r3, [r2, #48] ; 0x30
8000716: 4b26 ldr r3, [pc, #152] ; (80007b0 <MX_GPIO_Init+0xc0>)
8000718: 6b1b ldr r3, [r3, #48] ; 0x30
800071a: f003 0301 and.w r3, r3, #1
800071e: 60bb str r3, [r7, #8]
8000720: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000722: 2300 movs r3, #0
8000724: 607b str r3, [r7, #4]
8000726: 4b22 ldr r3, [pc, #136] ; (80007b0 <MX_GPIO_Init+0xc0>)
8000728: 6b1b ldr r3, [r3, #48] ; 0x30
800072a: 4a21 ldr r2, [pc, #132] ; (80007b0 <MX_GPIO_Init+0xc0>)
800072c: f043 0302 orr.w r3, r3, #2
8000730: 6313 str r3, [r2, #48] ; 0x30
8000732: 4b1f ldr r3, [pc, #124] ; (80007b0 <MX_GPIO_Init+0xc0>)
8000734: 6b1b ldr r3, [r3, #48] ; 0x30
8000736: f003 0302 and.w r3, r3, #2
800073a: 607b str r3, [r7, #4]
800073c: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOC_CLK_ENABLE();
800073e: 2300 movs r3, #0
8000740: 603b str r3, [r7, #0]
8000742: 4b1b ldr r3, [pc, #108] ; (80007b0 <MX_GPIO_Init+0xc0>)
8000744: 6b1b ldr r3, [r3, #48] ; 0x30
8000746: 4a1a ldr r2, [pc, #104] ; (80007b0 <MX_GPIO_Init+0xc0>)
8000748: f043 0304 orr.w r3, r3, #4
800074c: 6313 str r3, [r2, #48] ; 0x30
800074e: 4b18 ldr r3, [pc, #96] ; (80007b0 <MX_GPIO_Init+0xc0>)
8000750: 6b1b ldr r3, [r3, #48] ; 0x30
8000752: f003 0304 and.w r3, r3, #4
8000756: 603b str r3, [r7, #0]
8000758: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET);
800075a: 2200 movs r2, #0
800075c: f44f 5180 mov.w r1, #4096 ; 0x1000
8000760: 4814 ldr r0, [pc, #80] ; (80007b4 <MX_GPIO_Init+0xc4>)
8000762: f001 f879 bl 8001858 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PB12 */
GPIO_InitStruct.Pin = GPIO_PIN_12;
8000766: f44f 5380 mov.w r3, #4096 ; 0x1000
800076a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800076c: 2301 movs r3, #1
800076e: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000770: 2300 movs r3, #0
8000772: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000774: 2303 movs r3, #3
8000776: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000778: f107 030c add.w r3, r7, #12
800077c: 4619 mov r1, r3
800077e: 480d ldr r0, [pc, #52] ; (80007b4 <MX_GPIO_Init+0xc4>)
8000780: f000 fece bl 8001520 <HAL_GPIO_Init>
/*Configure GPIO pins : PC10 PC11 PC12 */
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
8000784: f44f 53e0 mov.w r3, #7168 ; 0x1c00
8000788: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800078a: 2302 movs r3, #2
800078c: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800078e: 2300 movs r3, #0
8000790: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000792: 2303 movs r3, #3
8000794: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
8000796: 2306 movs r3, #6
8000798: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800079a: f107 030c add.w r3, r7, #12
800079e: 4619 mov r1, r3
80007a0: 4805 ldr r0, [pc, #20] ; (80007b8 <MX_GPIO_Init+0xc8>)
80007a2: f000 febd bl 8001520 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
80007a6: bf00 nop
80007a8: 3720 adds r7, #32
80007aa: 46bd mov sp, r7
80007ac: bd80 pop {r7, pc}
80007ae: bf00 nop
80007b0: 40023800 .word 0x40023800
80007b4: 40020400 .word 0x40020400
80007b8: 40020800 .word 0x40020800
080007bc <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
80007bc: b480 push {r7}
80007be: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80007c0: b672 cpsid i
}
80007c2: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80007c4: e7fe b.n 80007c4 <Error_Handler+0x8>
...
080007c8 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80007c8: b480 push {r7}
80007ca: b083 sub sp, #12
80007cc: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80007ce: 2300 movs r3, #0
80007d0: 607b str r3, [r7, #4]
80007d2: 4b10 ldr r3, [pc, #64] ; (8000814 <HAL_MspInit+0x4c>)
80007d4: 6c5b ldr r3, [r3, #68] ; 0x44
80007d6: 4a0f ldr r2, [pc, #60] ; (8000814 <HAL_MspInit+0x4c>)
80007d8: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80007dc: 6453 str r3, [r2, #68] ; 0x44
80007de: 4b0d ldr r3, [pc, #52] ; (8000814 <HAL_MspInit+0x4c>)
80007e0: 6c5b ldr r3, [r3, #68] ; 0x44
80007e2: f403 4380 and.w r3, r3, #16384 ; 0x4000
80007e6: 607b str r3, [r7, #4]
80007e8: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80007ea: 2300 movs r3, #0
80007ec: 603b str r3, [r7, #0]
80007ee: 4b09 ldr r3, [pc, #36] ; (8000814 <HAL_MspInit+0x4c>)
80007f0: 6c1b ldr r3, [r3, #64] ; 0x40
80007f2: 4a08 ldr r2, [pc, #32] ; (8000814 <HAL_MspInit+0x4c>)
80007f4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80007f8: 6413 str r3, [r2, #64] ; 0x40
80007fa: 4b06 ldr r3, [pc, #24] ; (8000814 <HAL_MspInit+0x4c>)
80007fc: 6c1b ldr r3, [r3, #64] ; 0x40
80007fe: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000802: 603b str r3, [r7, #0]
8000804: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000806: bf00 nop
8000808: 370c adds r7, #12
800080a: 46bd mov sp, r7
800080c: f85d 7b04 ldr.w r7, [sp], #4
8000810: 4770 bx lr
8000812: bf00 nop
8000814: 40023800 .word 0x40023800
08000818 <HAL_CAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
8000818: b580 push {r7, lr}
800081a: b08a sub sp, #40 ; 0x28
800081c: af00 add r7, sp, #0
800081e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000820: f107 0314 add.w r3, r7, #20
8000824: 2200 movs r2, #0
8000826: 601a str r2, [r3, #0]
8000828: 605a str r2, [r3, #4]
800082a: 609a str r2, [r3, #8]
800082c: 60da str r2, [r3, #12]
800082e: 611a str r2, [r3, #16]
if(hcan->Instance==CAN1)
8000830: 687b ldr r3, [r7, #4]
8000832: 681b ldr r3, [r3, #0]
8000834: 4a19 ldr r2, [pc, #100] ; (800089c <HAL_CAN_MspInit+0x84>)
8000836: 4293 cmp r3, r2
8000838: d12c bne.n 8000894 <HAL_CAN_MspInit+0x7c>
{
/* USER CODE BEGIN CAN1_MspInit 0 */
/* USER CODE END CAN1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
800083a: 2300 movs r3, #0
800083c: 613b str r3, [r7, #16]
800083e: 4b18 ldr r3, [pc, #96] ; (80008a0 <HAL_CAN_MspInit+0x88>)
8000840: 6c1b ldr r3, [r3, #64] ; 0x40
8000842: 4a17 ldr r2, [pc, #92] ; (80008a0 <HAL_CAN_MspInit+0x88>)
8000844: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8000848: 6413 str r3, [r2, #64] ; 0x40
800084a: 4b15 ldr r3, [pc, #84] ; (80008a0 <HAL_CAN_MspInit+0x88>)
800084c: 6c1b ldr r3, [r3, #64] ; 0x40
800084e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8000852: 613b str r3, [r7, #16]
8000854: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000856: 2300 movs r3, #0
8000858: 60fb str r3, [r7, #12]
800085a: 4b11 ldr r3, [pc, #68] ; (80008a0 <HAL_CAN_MspInit+0x88>)
800085c: 6b1b ldr r3, [r3, #48] ; 0x30
800085e: 4a10 ldr r2, [pc, #64] ; (80008a0 <HAL_CAN_MspInit+0x88>)
8000860: f043 0301 orr.w r3, r3, #1
8000864: 6313 str r3, [r2, #48] ; 0x30
8000866: 4b0e ldr r3, [pc, #56] ; (80008a0 <HAL_CAN_MspInit+0x88>)
8000868: 6b1b ldr r3, [r3, #48] ; 0x30
800086a: f003 0301 and.w r3, r3, #1
800086e: 60fb str r3, [r7, #12]
8000870: 68fb ldr r3, [r7, #12]
/**CAN1 GPIO Configuration
PA11 ------> CAN1_RX
PA12 ------> CAN1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
8000872: f44f 53c0 mov.w r3, #6144 ; 0x1800
8000876: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000878: 2302 movs r3, #2
800087a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800087c: 2300 movs r3, #0
800087e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000880: 2303 movs r3, #3
8000882: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
8000884: 2309 movs r3, #9
8000886: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000888: f107 0314 add.w r3, r7, #20
800088c: 4619 mov r1, r3
800088e: 4805 ldr r0, [pc, #20] ; (80008a4 <HAL_CAN_MspInit+0x8c>)
8000890: f000 fe46 bl 8001520 <HAL_GPIO_Init>
/* USER CODE BEGIN CAN1_MspInit 1 */
/* USER CODE END CAN1_MspInit 1 */
}
}
8000894: bf00 nop
8000896: 3728 adds r7, #40 ; 0x28
8000898: 46bd mov sp, r7
800089a: bd80 pop {r7, pc}
800089c: 40006400 .word 0x40006400
80008a0: 40023800 .word 0x40023800
80008a4: 40020000 .word 0x40020000
080008a8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
80008a8: b580 push {r7, lr}
80008aa: b08a sub sp, #40 ; 0x28
80008ac: af00 add r7, sp, #0
80008ae: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80008b0: f107 0314 add.w r3, r7, #20
80008b4: 2200 movs r2, #0
80008b6: 601a str r2, [r3, #0]
80008b8: 605a str r2, [r3, #4]
80008ba: 609a str r2, [r3, #8]
80008bc: 60da str r2, [r3, #12]
80008be: 611a str r2, [r3, #16]
if(huart->Instance==UART4)
80008c0: 687b ldr r3, [r7, #4]
80008c2: 681b ldr r3, [r3, #0]
80008c4: 4a19 ldr r2, [pc, #100] ; (800092c <HAL_UART_MspInit+0x84>)
80008c6: 4293 cmp r3, r2
80008c8: d12b bne.n 8000922 <HAL_UART_MspInit+0x7a>
{
/* USER CODE BEGIN UART4_MspInit 0 */
/* USER CODE END UART4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_UART4_CLK_ENABLE();
80008ca: 2300 movs r3, #0
80008cc: 613b str r3, [r7, #16]
80008ce: 4b18 ldr r3, [pc, #96] ; (8000930 <HAL_UART_MspInit+0x88>)
80008d0: 6c1b ldr r3, [r3, #64] ; 0x40
80008d2: 4a17 ldr r2, [pc, #92] ; (8000930 <HAL_UART_MspInit+0x88>)
80008d4: f443 2300 orr.w r3, r3, #524288 ; 0x80000
80008d8: 6413 str r3, [r2, #64] ; 0x40
80008da: 4b15 ldr r3, [pc, #84] ; (8000930 <HAL_UART_MspInit+0x88>)
80008dc: 6c1b ldr r3, [r3, #64] ; 0x40
80008de: f403 2300 and.w r3, r3, #524288 ; 0x80000
80008e2: 613b str r3, [r7, #16]
80008e4: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80008e6: 2300 movs r3, #0
80008e8: 60fb str r3, [r7, #12]
80008ea: 4b11 ldr r3, [pc, #68] ; (8000930 <HAL_UART_MspInit+0x88>)
80008ec: 6b1b ldr r3, [r3, #48] ; 0x30
80008ee: 4a10 ldr r2, [pc, #64] ; (8000930 <HAL_UART_MspInit+0x88>)
80008f0: f043 0301 orr.w r3, r3, #1
80008f4: 6313 str r3, [r2, #48] ; 0x30
80008f6: 4b0e ldr r3, [pc, #56] ; (8000930 <HAL_UART_MspInit+0x88>)
80008f8: 6b1b ldr r3, [r3, #48] ; 0x30
80008fa: f003 0301 and.w r3, r3, #1
80008fe: 60fb str r3, [r7, #12]
8000900: 68fb ldr r3, [r7, #12]
/**UART4 GPIO Configuration
PA0-WKUP ------> UART4_TX
PA1 ------> UART4_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
8000902: 2303 movs r3, #3
8000904: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000906: 2302 movs r3, #2
8000908: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800090a: 2300 movs r3, #0
800090c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800090e: 2303 movs r3, #3
8000910: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
8000912: 2308 movs r3, #8
8000914: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000916: f107 0314 add.w r3, r7, #20
800091a: 4619 mov r1, r3
800091c: 4805 ldr r0, [pc, #20] ; (8000934 <HAL_UART_MspInit+0x8c>)
800091e: f000 fdff bl 8001520 <HAL_GPIO_Init>
/* USER CODE BEGIN UART4_MspInit 1 */
/* USER CODE END UART4_MspInit 1 */
}
}
8000922: bf00 nop
8000924: 3728 adds r7, #40 ; 0x28
8000926: 46bd mov sp, r7
8000928: bd80 pop {r7, pc}
800092a: bf00 nop
800092c: 40004c00 .word 0x40004c00
8000930: 40023800 .word 0x40023800
8000934: 40020000 .word 0x40020000
08000938 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000938: b480 push {r7}
800093a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800093c: e7fe b.n 800093c <NMI_Handler+0x4>
0800093e <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800093e: b480 push {r7}
8000940: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000942: e7fe b.n 8000942 <HardFault_Handler+0x4>
08000944 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000944: b480 push {r7}
8000946: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000948: e7fe b.n 8000948 <MemManage_Handler+0x4>
0800094a <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800094a: b480 push {r7}
800094c: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800094e: e7fe b.n 800094e <BusFault_Handler+0x4>
08000950 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000950: b480 push {r7}
8000952: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000954: e7fe b.n 8000954 <UsageFault_Handler+0x4>
08000956 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000956: b480 push {r7}
8000958: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800095a: bf00 nop
800095c: 46bd mov sp, r7
800095e: f85d 7b04 ldr.w r7, [sp], #4
8000962: 4770 bx lr
08000964 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000964: b480 push {r7}
8000966: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000968: bf00 nop
800096a: 46bd mov sp, r7
800096c: f85d 7b04 ldr.w r7, [sp], #4
8000970: 4770 bx lr
08000972 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000972: b480 push {r7}
8000974: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000976: bf00 nop
8000978: 46bd mov sp, r7
800097a: f85d 7b04 ldr.w r7, [sp], #4
800097e: 4770 bx lr
08000980 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8000980: b580 push {r7, lr}
8000982: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8000984: f000 f890 bl 8000aa8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8000988: bf00 nop
800098a: bd80 pop {r7, pc}
0800098c <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
800098c: b480 push {r7}
800098e: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000990: 4b06 ldr r3, [pc, #24] ; (80009ac <SystemInit+0x20>)
8000992: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000996: 4a05 ldr r2, [pc, #20] ; (80009ac <SystemInit+0x20>)
8000998: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
800099c: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80009a0: bf00 nop
80009a2: 46bd mov sp, r7
80009a4: f85d 7b04 ldr.w r7, [sp], #4
80009a8: 4770 bx lr
80009aa: bf00 nop
80009ac: e000ed00 .word 0xe000ed00
080009b0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
80009b0: f8df d034 ldr.w sp, [pc, #52] ; 80009e8 <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80009b4: 480d ldr r0, [pc, #52] ; (80009ec <LoopFillZerobss+0x16>)
ldr r1, =_edata
80009b6: 490e ldr r1, [pc, #56] ; (80009f0 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
80009b8: 4a0e ldr r2, [pc, #56] ; (80009f4 <LoopFillZerobss+0x1e>)
movs r3, #0
80009ba: 2300 movs r3, #0
b LoopCopyDataInit
80009bc: e002 b.n 80009c4 <LoopCopyDataInit>
080009be <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80009be: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80009c0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80009c2: 3304 adds r3, #4
080009c4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80009c4: 18c4 adds r4, r0, r3
cmp r4, r1
80009c6: 428c cmp r4, r1
bcc CopyDataInit
80009c8: d3f9 bcc.n 80009be <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80009ca: 4a0b ldr r2, [pc, #44] ; (80009f8 <LoopFillZerobss+0x22>)
ldr r4, =_ebss
80009cc: 4c0b ldr r4, [pc, #44] ; (80009fc <LoopFillZerobss+0x26>)
movs r3, #0
80009ce: 2300 movs r3, #0
b LoopFillZerobss
80009d0: e001 b.n 80009d6 <LoopFillZerobss>
080009d2 <FillZerobss>:
FillZerobss:
str r3, [r2]
80009d2: 6013 str r3, [r2, #0]
adds r2, r2, #4
80009d4: 3204 adds r2, #4
080009d6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80009d6: 42a2 cmp r2, r4
bcc FillZerobss
80009d8: d3fb bcc.n 80009d2 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
80009da: f7ff ffd7 bl 800098c <SystemInit>
/* Call static constructors */
bl __libc_init_array
80009de: f002 f8c3 bl 8002b68 <__libc_init_array>
/* Call the application's entry point.*/
bl main
80009e2: f7ff fdaf bl 8000544 <main>
bx lr
80009e6: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
80009e8: 20020000 .word 0x20020000
ldr r0, =_sdata
80009ec: 20000000 .word 0x20000000
ldr r1, =_edata
80009f0: 2000000c .word 0x2000000c
ldr r2, =_sidata
80009f4: 08002cac .word 0x08002cac
ldr r2, =_sbss
80009f8: 2000000c .word 0x2000000c
ldr r4, =_ebss
80009fc: 20000098 .word 0x20000098
08000a00 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000a00: e7fe b.n 8000a00 <ADC_IRQHandler>
...
08000a04 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000a04: b580 push {r7, lr}
8000a06: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8000a08: 4b0e ldr r3, [pc, #56] ; (8000a44 <HAL_Init+0x40>)
8000a0a: 681b ldr r3, [r3, #0]
8000a0c: 4a0d ldr r2, [pc, #52] ; (8000a44 <HAL_Init+0x40>)
8000a0e: f443 7300 orr.w r3, r3, #512 ; 0x200
8000a12: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000a14: 4b0b ldr r3, [pc, #44] ; (8000a44 <HAL_Init+0x40>)
8000a16: 681b ldr r3, [r3, #0]
8000a18: 4a0a ldr r2, [pc, #40] ; (8000a44 <HAL_Init+0x40>)
8000a1a: f443 6380 orr.w r3, r3, #1024 ; 0x400
8000a1e: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000a20: 4b08 ldr r3, [pc, #32] ; (8000a44 <HAL_Init+0x40>)
8000a22: 681b ldr r3, [r3, #0]
8000a24: 4a07 ldr r2, [pc, #28] ; (8000a44 <HAL_Init+0x40>)
8000a26: f443 7380 orr.w r3, r3, #256 ; 0x100
8000a2a: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000a2c: 2003 movs r0, #3
8000a2e: f000 fd43 bl 80014b8 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000a32: 200f movs r0, #15
8000a34: f000 f808 bl 8000a48 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000a38: f7ff fec6 bl 80007c8 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000a3c: 2300 movs r3, #0
}
8000a3e: 4618 mov r0, r3
8000a40: bd80 pop {r7, pc}
8000a42: bf00 nop
8000a44: 40023c00 .word 0x40023c00
08000a48 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000a48: b580 push {r7, lr}
8000a4a: b082 sub sp, #8
8000a4c: af00 add r7, sp, #0
8000a4e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000a50: 4b12 ldr r3, [pc, #72] ; (8000a9c <HAL_InitTick+0x54>)
8000a52: 681a ldr r2, [r3, #0]
8000a54: 4b12 ldr r3, [pc, #72] ; (8000aa0 <HAL_InitTick+0x58>)
8000a56: 781b ldrb r3, [r3, #0]
8000a58: 4619 mov r1, r3
8000a5a: f44f 737a mov.w r3, #1000 ; 0x3e8
8000a5e: fbb3 f3f1 udiv r3, r3, r1
8000a62: fbb2 f3f3 udiv r3, r2, r3
8000a66: 4618 mov r0, r3
8000a68: f000 fd4d bl 8001506 <HAL_SYSTICK_Config>
8000a6c: 4603 mov r3, r0
8000a6e: 2b00 cmp r3, #0
8000a70: d001 beq.n 8000a76 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000a72: 2301 movs r3, #1
8000a74: e00e b.n 8000a94 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000a76: 687b ldr r3, [r7, #4]
8000a78: 2b0f cmp r3, #15
8000a7a: d80a bhi.n 8000a92 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000a7c: 2200 movs r2, #0
8000a7e: 6879 ldr r1, [r7, #4]
8000a80: f04f 30ff mov.w r0, #4294967295
8000a84: f000 fd23 bl 80014ce <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000a88: 4a06 ldr r2, [pc, #24] ; (8000aa4 <HAL_InitTick+0x5c>)
8000a8a: 687b ldr r3, [r7, #4]
8000a8c: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8000a8e: 2300 movs r3, #0
8000a90: e000 b.n 8000a94 <HAL_InitTick+0x4c>
return HAL_ERROR;
8000a92: 2301 movs r3, #1
}
8000a94: 4618 mov r0, r3
8000a96: 3708 adds r7, #8
8000a98: 46bd mov sp, r7
8000a9a: bd80 pop {r7, pc}
8000a9c: 20000000 .word 0x20000000
8000aa0: 20000008 .word 0x20000008
8000aa4: 20000004 .word 0x20000004
08000aa8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000aa8: b480 push {r7}
8000aaa: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000aac: 4b06 ldr r3, [pc, #24] ; (8000ac8 <HAL_IncTick+0x20>)
8000aae: 781b ldrb r3, [r3, #0]
8000ab0: 461a mov r2, r3
8000ab2: 4b06 ldr r3, [pc, #24] ; (8000acc <HAL_IncTick+0x24>)
8000ab4: 681b ldr r3, [r3, #0]
8000ab6: 4413 add r3, r2
8000ab8: 4a04 ldr r2, [pc, #16] ; (8000acc <HAL_IncTick+0x24>)
8000aba: 6013 str r3, [r2, #0]
}
8000abc: bf00 nop
8000abe: 46bd mov sp, r7
8000ac0: f85d 7b04 ldr.w r7, [sp], #4
8000ac4: 4770 bx lr
8000ac6: bf00 nop
8000ac8: 20000008 .word 0x20000008
8000acc: 20000094 .word 0x20000094
08000ad0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000ad0: b480 push {r7}
8000ad2: af00 add r7, sp, #0
return uwTick;
8000ad4: 4b03 ldr r3, [pc, #12] ; (8000ae4 <HAL_GetTick+0x14>)
8000ad6: 681b ldr r3, [r3, #0]
}
8000ad8: 4618 mov r0, r3
8000ada: 46bd mov sp, r7
8000adc: f85d 7b04 ldr.w r7, [sp], #4
8000ae0: 4770 bx lr
8000ae2: bf00 nop
8000ae4: 20000094 .word 0x20000094
08000ae8 <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
8000ae8: b580 push {r7, lr}
8000aea: b084 sub sp, #16
8000aec: af00 add r7, sp, #0
8000aee: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
8000af0: 687b ldr r3, [r7, #4]
8000af2: 2b00 cmp r3, #0
8000af4: d101 bne.n 8000afa <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
8000af6: 2301 movs r3, #1
8000af8: e0ed b.n 8000cd6 <HAL_CAN_Init+0x1ee>
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
}
#else
if (hcan->State == HAL_CAN_STATE_RESET)
8000afa: 687b ldr r3, [r7, #4]
8000afc: f893 3020 ldrb.w r3, [r3, #32]
8000b00: b2db uxtb r3, r3
8000b02: 2b00 cmp r3, #0
8000b04: d102 bne.n 8000b0c <HAL_CAN_Init+0x24>
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
8000b06: 6878 ldr r0, [r7, #4]
8000b08: f7ff fe86 bl 8000818 <HAL_CAN_MspInit>
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8000b0c: 687b ldr r3, [r7, #4]
8000b0e: 681b ldr r3, [r3, #0]
8000b10: 681a ldr r2, [r3, #0]
8000b12: 687b ldr r3, [r7, #4]
8000b14: 681b ldr r3, [r3, #0]
8000b16: f042 0201 orr.w r2, r2, #1
8000b1a: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000b1c: f7ff ffd8 bl 8000ad0 <HAL_GetTick>
8000b20: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000b22: e012 b.n 8000b4a <HAL_CAN_Init+0x62>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000b24: f7ff ffd4 bl 8000ad0 <HAL_GetTick>
8000b28: 4602 mov r2, r0
8000b2a: 68fb ldr r3, [r7, #12]
8000b2c: 1ad3 subs r3, r2, r3
8000b2e: 2b0a cmp r3, #10
8000b30: d90b bls.n 8000b4a <HAL_CAN_Init+0x62>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000b32: 687b ldr r3, [r7, #4]
8000b34: 6a5b ldr r3, [r3, #36] ; 0x24
8000b36: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8000b3a: 687b ldr r3, [r7, #4]
8000b3c: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000b3e: 687b ldr r3, [r7, #4]
8000b40: 2205 movs r2, #5
8000b42: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000b46: 2301 movs r3, #1
8000b48: e0c5 b.n 8000cd6 <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000b4a: 687b ldr r3, [r7, #4]
8000b4c: 681b ldr r3, [r3, #0]
8000b4e: 685b ldr r3, [r3, #4]
8000b50: f003 0301 and.w r3, r3, #1
8000b54: 2b00 cmp r3, #0
8000b56: d0e5 beq.n 8000b24 <HAL_CAN_Init+0x3c>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
8000b58: 687b ldr r3, [r7, #4]
8000b5a: 681b ldr r3, [r3, #0]
8000b5c: 681a ldr r2, [r3, #0]
8000b5e: 687b ldr r3, [r7, #4]
8000b60: 681b ldr r3, [r3, #0]
8000b62: f022 0202 bic.w r2, r2, #2
8000b66: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000b68: f7ff ffb2 bl 8000ad0 <HAL_GetTick>
8000b6c: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000b6e: e012 b.n 8000b96 <HAL_CAN_Init+0xae>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000b70: f7ff ffae bl 8000ad0 <HAL_GetTick>
8000b74: 4602 mov r2, r0
8000b76: 68fb ldr r3, [r7, #12]
8000b78: 1ad3 subs r3, r2, r3
8000b7a: 2b0a cmp r3, #10
8000b7c: d90b bls.n 8000b96 <HAL_CAN_Init+0xae>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000b7e: 687b ldr r3, [r7, #4]
8000b80: 6a5b ldr r3, [r3, #36] ; 0x24
8000b82: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8000b86: 687b ldr r3, [r7, #4]
8000b88: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000b8a: 687b ldr r3, [r7, #4]
8000b8c: 2205 movs r2, #5
8000b8e: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000b92: 2301 movs r3, #1
8000b94: e09f b.n 8000cd6 <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000b96: 687b ldr r3, [r7, #4]
8000b98: 681b ldr r3, [r3, #0]
8000b9a: 685b ldr r3, [r3, #4]
8000b9c: f003 0302 and.w r3, r3, #2
8000ba0: 2b00 cmp r3, #0
8000ba2: d1e5 bne.n 8000b70 <HAL_CAN_Init+0x88>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
8000ba4: 687b ldr r3, [r7, #4]
8000ba6: 7e1b ldrb r3, [r3, #24]
8000ba8: 2b01 cmp r3, #1
8000baa: d108 bne.n 8000bbe <HAL_CAN_Init+0xd6>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000bac: 687b ldr r3, [r7, #4]
8000bae: 681b ldr r3, [r3, #0]
8000bb0: 681a ldr r2, [r3, #0]
8000bb2: 687b ldr r3, [r7, #4]
8000bb4: 681b ldr r3, [r3, #0]
8000bb6: f042 0280 orr.w r2, r2, #128 ; 0x80
8000bba: 601a str r2, [r3, #0]
8000bbc: e007 b.n 8000bce <HAL_CAN_Init+0xe6>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000bbe: 687b ldr r3, [r7, #4]
8000bc0: 681b ldr r3, [r3, #0]
8000bc2: 681a ldr r2, [r3, #0]
8000bc4: 687b ldr r3, [r7, #4]
8000bc6: 681b ldr r3, [r3, #0]
8000bc8: f022 0280 bic.w r2, r2, #128 ; 0x80
8000bcc: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
8000bce: 687b ldr r3, [r7, #4]
8000bd0: 7e5b ldrb r3, [r3, #25]
8000bd2: 2b01 cmp r3, #1
8000bd4: d108 bne.n 8000be8 <HAL_CAN_Init+0x100>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000bd6: 687b ldr r3, [r7, #4]
8000bd8: 681b ldr r3, [r3, #0]
8000bda: 681a ldr r2, [r3, #0]
8000bdc: 687b ldr r3, [r7, #4]
8000bde: 681b ldr r3, [r3, #0]
8000be0: f042 0240 orr.w r2, r2, #64 ; 0x40
8000be4: 601a str r2, [r3, #0]
8000be6: e007 b.n 8000bf8 <HAL_CAN_Init+0x110>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000be8: 687b ldr r3, [r7, #4]
8000bea: 681b ldr r3, [r3, #0]
8000bec: 681a ldr r2, [r3, #0]
8000bee: 687b ldr r3, [r7, #4]
8000bf0: 681b ldr r3, [r3, #0]
8000bf2: f022 0240 bic.w r2, r2, #64 ; 0x40
8000bf6: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
8000bf8: 687b ldr r3, [r7, #4]
8000bfa: 7e9b ldrb r3, [r3, #26]
8000bfc: 2b01 cmp r3, #1
8000bfe: d108 bne.n 8000c12 <HAL_CAN_Init+0x12a>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000c00: 687b ldr r3, [r7, #4]
8000c02: 681b ldr r3, [r3, #0]
8000c04: 681a ldr r2, [r3, #0]
8000c06: 687b ldr r3, [r7, #4]
8000c08: 681b ldr r3, [r3, #0]
8000c0a: f042 0220 orr.w r2, r2, #32
8000c0e: 601a str r2, [r3, #0]
8000c10: e007 b.n 8000c22 <HAL_CAN_Init+0x13a>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000c12: 687b ldr r3, [r7, #4]
8000c14: 681b ldr r3, [r3, #0]
8000c16: 681a ldr r2, [r3, #0]
8000c18: 687b ldr r3, [r7, #4]
8000c1a: 681b ldr r3, [r3, #0]
8000c1c: f022 0220 bic.w r2, r2, #32
8000c20: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
8000c22: 687b ldr r3, [r7, #4]
8000c24: 7edb ldrb r3, [r3, #27]
8000c26: 2b01 cmp r3, #1
8000c28: d108 bne.n 8000c3c <HAL_CAN_Init+0x154>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000c2a: 687b ldr r3, [r7, #4]
8000c2c: 681b ldr r3, [r3, #0]
8000c2e: 681a ldr r2, [r3, #0]
8000c30: 687b ldr r3, [r7, #4]
8000c32: 681b ldr r3, [r3, #0]
8000c34: f022 0210 bic.w r2, r2, #16
8000c38: 601a str r2, [r3, #0]
8000c3a: e007 b.n 8000c4c <HAL_CAN_Init+0x164>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000c3c: 687b ldr r3, [r7, #4]
8000c3e: 681b ldr r3, [r3, #0]
8000c40: 681a ldr r2, [r3, #0]
8000c42: 687b ldr r3, [r7, #4]
8000c44: 681b ldr r3, [r3, #0]
8000c46: f042 0210 orr.w r2, r2, #16
8000c4a: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
8000c4c: 687b ldr r3, [r7, #4]
8000c4e: 7f1b ldrb r3, [r3, #28]
8000c50: 2b01 cmp r3, #1
8000c52: d108 bne.n 8000c66 <HAL_CAN_Init+0x17e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000c54: 687b ldr r3, [r7, #4]
8000c56: 681b ldr r3, [r3, #0]
8000c58: 681a ldr r2, [r3, #0]
8000c5a: 687b ldr r3, [r7, #4]
8000c5c: 681b ldr r3, [r3, #0]
8000c5e: f042 0208 orr.w r2, r2, #8
8000c62: 601a str r2, [r3, #0]
8000c64: e007 b.n 8000c76 <HAL_CAN_Init+0x18e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000c66: 687b ldr r3, [r7, #4]
8000c68: 681b ldr r3, [r3, #0]
8000c6a: 681a ldr r2, [r3, #0]
8000c6c: 687b ldr r3, [r7, #4]
8000c6e: 681b ldr r3, [r3, #0]
8000c70: f022 0208 bic.w r2, r2, #8
8000c74: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
8000c76: 687b ldr r3, [r7, #4]
8000c78: 7f5b ldrb r3, [r3, #29]
8000c7a: 2b01 cmp r3, #1
8000c7c: d108 bne.n 8000c90 <HAL_CAN_Init+0x1a8>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000c7e: 687b ldr r3, [r7, #4]
8000c80: 681b ldr r3, [r3, #0]
8000c82: 681a ldr r2, [r3, #0]
8000c84: 687b ldr r3, [r7, #4]
8000c86: 681b ldr r3, [r3, #0]
8000c88: f042 0204 orr.w r2, r2, #4
8000c8c: 601a str r2, [r3, #0]
8000c8e: e007 b.n 8000ca0 <HAL_CAN_Init+0x1b8>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000c90: 687b ldr r3, [r7, #4]
8000c92: 681b ldr r3, [r3, #0]
8000c94: 681a ldr r2, [r3, #0]
8000c96: 687b ldr r3, [r7, #4]
8000c98: 681b ldr r3, [r3, #0]
8000c9a: f022 0204 bic.w r2, r2, #4
8000c9e: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
8000ca0: 687b ldr r3, [r7, #4]
8000ca2: 689a ldr r2, [r3, #8]
8000ca4: 687b ldr r3, [r7, #4]
8000ca6: 68db ldr r3, [r3, #12]
8000ca8: 431a orrs r2, r3
8000caa: 687b ldr r3, [r7, #4]
8000cac: 691b ldr r3, [r3, #16]
8000cae: 431a orrs r2, r3
8000cb0: 687b ldr r3, [r7, #4]
8000cb2: 695b ldr r3, [r3, #20]
8000cb4: ea42 0103 orr.w r1, r2, r3
8000cb8: 687b ldr r3, [r7, #4]
8000cba: 685b ldr r3, [r3, #4]
8000cbc: 1e5a subs r2, r3, #1
8000cbe: 687b ldr r3, [r7, #4]
8000cc0: 681b ldr r3, [r3, #0]
8000cc2: 430a orrs r2, r1
8000cc4: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8000cc6: 687b ldr r3, [r7, #4]
8000cc8: 2200 movs r2, #0
8000cca: 625a str r2, [r3, #36] ; 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
8000ccc: 687b ldr r3, [r7, #4]
8000cce: 2201 movs r2, #1
8000cd0: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
8000cd4: 2300 movs r3, #0
}
8000cd6: 4618 mov r0, r3
8000cd8: 3710 adds r7, #16
8000cda: 46bd mov sp, r7
8000cdc: bd80 pop {r7, pc}
...
08000ce0 <HAL_CAN_ConfigFilter>:
* @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
{
8000ce0: b480 push {r7}
8000ce2: b087 sub sp, #28
8000ce4: af00 add r7, sp, #0
8000ce6: 6078 str r0, [r7, #4]
8000ce8: 6039 str r1, [r7, #0]
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
8000cea: 687b ldr r3, [r7, #4]
8000cec: 681b ldr r3, [r3, #0]
8000cee: 617b str r3, [r7, #20]
HAL_CAN_StateTypeDef state = hcan->State;
8000cf0: 687b ldr r3, [r7, #4]
8000cf2: f893 3020 ldrb.w r3, [r3, #32]
8000cf6: 74fb strb r3, [r7, #19]
if ((state == HAL_CAN_STATE_READY) ||
8000cf8: 7cfb ldrb r3, [r7, #19]
8000cfa: 2b01 cmp r3, #1
8000cfc: d003 beq.n 8000d06 <HAL_CAN_ConfigFilter+0x26>
8000cfe: 7cfb ldrb r3, [r7, #19]
8000d00: 2b02 cmp r3, #2
8000d02: f040 80be bne.w 8000e82 <HAL_CAN_ConfigFilter+0x1a2>
assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
}
#elif defined(CAN2)
/* CAN1 and CAN2 are dual instances with 28 common filters banks */
/* Select master instance to access the filter banks */
can_ip = CAN1;
8000d06: 4b65 ldr r3, [pc, #404] ; (8000e9c <HAL_CAN_ConfigFilter+0x1bc>)
8000d08: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
#endif
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
8000d0a: 697b ldr r3, [r7, #20]
8000d0c: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8000d10: f043 0201 orr.w r2, r3, #1
8000d14: 697b ldr r3, [r7, #20]
8000d16: f8c3 2200 str.w r2, [r3, #512] ; 0x200
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
}
#elif defined(CAN2)
/* Select the start filter number of CAN2 slave instance */
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
8000d1a: 697b ldr r3, [r7, #20]
8000d1c: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8000d20: f423 527c bic.w r2, r3, #16128 ; 0x3f00
8000d24: 697b ldr r3, [r7, #20]
8000d26: f8c3 2200 str.w r2, [r3, #512] ; 0x200
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
8000d2a: 697b ldr r3, [r7, #20]
8000d2c: f8d3 2200 ldr.w r2, [r3, #512] ; 0x200
8000d30: 683b ldr r3, [r7, #0]
8000d32: 6a5b ldr r3, [r3, #36] ; 0x24
8000d34: 021b lsls r3, r3, #8
8000d36: 431a orrs r2, r3
8000d38: 697b ldr r3, [r7, #20]
8000d3a: f8c3 2200 str.w r2, [r3, #512] ; 0x200
#endif
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
8000d3e: 683b ldr r3, [r7, #0]
8000d40: 695b ldr r3, [r3, #20]
8000d42: f003 031f and.w r3, r3, #31
8000d46: 2201 movs r2, #1
8000d48: fa02 f303 lsl.w r3, r2, r3
8000d4c: 60fb str r3, [r7, #12]
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
8000d4e: 697b ldr r3, [r7, #20]
8000d50: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c
8000d54: 68fb ldr r3, [r7, #12]
8000d56: 43db mvns r3, r3
8000d58: 401a ands r2, r3
8000d5a: 697b ldr r3, [r7, #20]
8000d5c: f8c3 221c str.w r2, [r3, #540] ; 0x21c
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
8000d60: 683b ldr r3, [r7, #0]
8000d62: 69db ldr r3, [r3, #28]
8000d64: 2b00 cmp r3, #0
8000d66: d123 bne.n 8000db0 <HAL_CAN_ConfigFilter+0xd0>
{
/* 16-bit scale for the filter */
CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
8000d68: 697b ldr r3, [r7, #20]
8000d6a: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c
8000d6e: 68fb ldr r3, [r7, #12]
8000d70: 43db mvns r3, r3
8000d72: 401a ands r2, r3
8000d74: 697b ldr r3, [r7, #20]
8000d76: f8c3 220c str.w r2, [r3, #524] ; 0x20c
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8000d7a: 683b ldr r3, [r7, #0]
8000d7c: 68db ldr r3, [r3, #12]
8000d7e: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8000d80: 683b ldr r3, [r7, #0]
8000d82: 685b ldr r3, [r3, #4]
8000d84: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000d86: 683a ldr r2, [r7, #0]
8000d88: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8000d8a: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000d8c: 697b ldr r3, [r7, #20]
8000d8e: 3248 adds r2, #72 ; 0x48
8000d90: f843 1032 str.w r1, [r3, r2, lsl #3]
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000d94: 683b ldr r3, [r7, #0]
8000d96: 689b ldr r3, [r3, #8]
8000d98: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
8000d9a: 683b ldr r3, [r7, #0]
8000d9c: 681b ldr r3, [r3, #0]
8000d9e: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000da0: 683b ldr r3, [r7, #0]
8000da2: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000da4: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000da6: 6979 ldr r1, [r7, #20]
8000da8: 3348 adds r3, #72 ; 0x48
8000daa: 00db lsls r3, r3, #3
8000dac: 440b add r3, r1
8000dae: 605a str r2, [r3, #4]
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
8000db0: 683b ldr r3, [r7, #0]
8000db2: 69db ldr r3, [r3, #28]
8000db4: 2b01 cmp r3, #1
8000db6: d122 bne.n 8000dfe <HAL_CAN_ConfigFilter+0x11e>
{
/* 32-bit scale for the filter */
SET_BIT(can_ip->FS1R, filternbrbitpos);
8000db8: 697b ldr r3, [r7, #20]
8000dba: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c
8000dbe: 68fb ldr r3, [r7, #12]
8000dc0: 431a orrs r2, r3
8000dc2: 697b ldr r3, [r7, #20]
8000dc4: f8c3 220c str.w r2, [r3, #524] ; 0x20c
/* 32-bit identifier or First 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8000dc8: 683b ldr r3, [r7, #0]
8000dca: 681b ldr r3, [r3, #0]
8000dcc: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8000dce: 683b ldr r3, [r7, #0]
8000dd0: 685b ldr r3, [r3, #4]
8000dd2: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000dd4: 683a ldr r2, [r7, #0]
8000dd6: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8000dd8: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000dda: 697b ldr r3, [r7, #20]
8000ddc: 3248 adds r2, #72 ; 0x48
8000dde: f843 1032 str.w r1, [r3, r2, lsl #3]
/* 32-bit mask or Second 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000de2: 683b ldr r3, [r7, #0]
8000de4: 689b ldr r3, [r3, #8]
8000de6: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
8000de8: 683b ldr r3, [r7, #0]
8000dea: 68db ldr r3, [r3, #12]
8000dec: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000dee: 683b ldr r3, [r7, #0]
8000df0: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000df2: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000df4: 6979 ldr r1, [r7, #20]
8000df6: 3348 adds r3, #72 ; 0x48
8000df8: 00db lsls r3, r3, #3
8000dfa: 440b add r3, r1
8000dfc: 605a str r2, [r3, #4]
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
8000dfe: 683b ldr r3, [r7, #0]
8000e00: 699b ldr r3, [r3, #24]
8000e02: 2b00 cmp r3, #0
8000e04: d109 bne.n 8000e1a <HAL_CAN_ConfigFilter+0x13a>
{
/* Id/Mask mode for the filter*/
CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
8000e06: 697b ldr r3, [r7, #20]
8000e08: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
8000e0c: 68fb ldr r3, [r7, #12]
8000e0e: 43db mvns r3, r3
8000e10: 401a ands r2, r3
8000e12: 697b ldr r3, [r7, #20]
8000e14: f8c3 2204 str.w r2, [r3, #516] ; 0x204
8000e18: e007 b.n 8000e2a <HAL_CAN_ConfigFilter+0x14a>
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/* Identifier list mode for the filter*/
SET_BIT(can_ip->FM1R, filternbrbitpos);
8000e1a: 697b ldr r3, [r7, #20]
8000e1c: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
8000e20: 68fb ldr r3, [r7, #12]
8000e22: 431a orrs r2, r3
8000e24: 697b ldr r3, [r7, #20]
8000e26: f8c3 2204 str.w r2, [r3, #516] ; 0x204
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
8000e2a: 683b ldr r3, [r7, #0]
8000e2c: 691b ldr r3, [r3, #16]
8000e2e: 2b00 cmp r3, #0
8000e30: d109 bne.n 8000e46 <HAL_CAN_ConfigFilter+0x166>
{
/* FIFO 0 assignation for the filter */
CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
8000e32: 697b ldr r3, [r7, #20]
8000e34: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214
8000e38: 68fb ldr r3, [r7, #12]
8000e3a: 43db mvns r3, r3
8000e3c: 401a ands r2, r3
8000e3e: 697b ldr r3, [r7, #20]
8000e40: f8c3 2214 str.w r2, [r3, #532] ; 0x214
8000e44: e007 b.n 8000e56 <HAL_CAN_ConfigFilter+0x176>
}
else
{
/* FIFO 1 assignation for the filter */
SET_BIT(can_ip->FFA1R, filternbrbitpos);
8000e46: 697b ldr r3, [r7, #20]
8000e48: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214
8000e4c: 68fb ldr r3, [r7, #12]
8000e4e: 431a orrs r2, r3
8000e50: 697b ldr r3, [r7, #20]
8000e52: f8c3 2214 str.w r2, [r3, #532] ; 0x214
}
/* Filter activation */
if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
8000e56: 683b ldr r3, [r7, #0]
8000e58: 6a1b ldr r3, [r3, #32]
8000e5a: 2b01 cmp r3, #1
8000e5c: d107 bne.n 8000e6e <HAL_CAN_ConfigFilter+0x18e>
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
8000e5e: 697b ldr r3, [r7, #20]
8000e60: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c
8000e64: 68fb ldr r3, [r7, #12]
8000e66: 431a orrs r2, r3
8000e68: 697b ldr r3, [r7, #20]
8000e6a: f8c3 221c str.w r2, [r3, #540] ; 0x21c
}
/* Leave the initialisation mode for the filter */
CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
8000e6e: 697b ldr r3, [r7, #20]
8000e70: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8000e74: f023 0201 bic.w r2, r3, #1
8000e78: 697b ldr r3, [r7, #20]
8000e7a: f8c3 2200 str.w r2, [r3, #512] ; 0x200
/* Return function status */
return HAL_OK;
8000e7e: 2300 movs r3, #0
8000e80: e006 b.n 8000e90 <HAL_CAN_ConfigFilter+0x1b0>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8000e82: 687b ldr r3, [r7, #4]
8000e84: 6a5b ldr r3, [r3, #36] ; 0x24
8000e86: f443 2280 orr.w r2, r3, #262144 ; 0x40000
8000e8a: 687b ldr r3, [r7, #4]
8000e8c: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000e8e: 2301 movs r3, #1
}
}
8000e90: 4618 mov r0, r3
8000e92: 371c adds r7, #28
8000e94: 46bd mov sp, r7
8000e96: f85d 7b04 ldr.w r7, [sp], #4
8000e9a: 4770 bx lr
8000e9c: 40006400 .word 0x40006400
08000ea0 <HAL_CAN_Start>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
8000ea0: b580 push {r7, lr}
8000ea2: b084 sub sp, #16
8000ea4: af00 add r7, sp, #0
8000ea6: 6078 str r0, [r7, #4]
uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
8000ea8: 687b ldr r3, [r7, #4]
8000eaa: f893 3020 ldrb.w r3, [r3, #32]
8000eae: b2db uxtb r3, r3
8000eb0: 2b01 cmp r3, #1
8000eb2: d12e bne.n 8000f12 <HAL_CAN_Start+0x72>
{
/* Change CAN peripheral state */
hcan->State = HAL_CAN_STATE_LISTENING;
8000eb4: 687b ldr r3, [r7, #4]
8000eb6: 2202 movs r2, #2
8000eb8: f883 2020 strb.w r2, [r3, #32]
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8000ebc: 687b ldr r3, [r7, #4]
8000ebe: 681b ldr r3, [r3, #0]
8000ec0: 681a ldr r2, [r3, #0]
8000ec2: 687b ldr r3, [r7, #4]
8000ec4: 681b ldr r3, [r3, #0]
8000ec6: f022 0201 bic.w r2, r2, #1
8000eca: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000ecc: f7ff fe00 bl 8000ad0 <HAL_GetTick>
8000ed0: 60f8 str r0, [r7, #12]
/* Wait the acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
8000ed2: e012 b.n 8000efa <HAL_CAN_Start+0x5a>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000ed4: f7ff fdfc bl 8000ad0 <HAL_GetTick>
8000ed8: 4602 mov r2, r0
8000eda: 68fb ldr r3, [r7, #12]
8000edc: 1ad3 subs r3, r2, r3
8000ede: 2b0a cmp r3, #10
8000ee0: d90b bls.n 8000efa <HAL_CAN_Start+0x5a>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000ee2: 687b ldr r3, [r7, #4]
8000ee4: 6a5b ldr r3, [r3, #36] ; 0x24
8000ee6: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8000eea: 687b ldr r3, [r7, #4]
8000eec: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000eee: 687b ldr r3, [r7, #4]
8000ef0: 2205 movs r2, #5
8000ef2: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000ef6: 2301 movs r3, #1
8000ef8: e012 b.n 8000f20 <HAL_CAN_Start+0x80>
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
8000efa: 687b ldr r3, [r7, #4]
8000efc: 681b ldr r3, [r3, #0]
8000efe: 685b ldr r3, [r3, #4]
8000f00: f003 0301 and.w r3, r3, #1
8000f04: 2b00 cmp r3, #0
8000f06: d1e5 bne.n 8000ed4 <HAL_CAN_Start+0x34>
}
}
/* Reset the CAN ErrorCode */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8000f08: 687b ldr r3, [r7, #4]
8000f0a: 2200 movs r2, #0
8000f0c: 625a str r2, [r3, #36] ; 0x24
/* Return function status */
return HAL_OK;
8000f0e: 2300 movs r3, #0
8000f10: e006 b.n 8000f20 <HAL_CAN_Start+0x80>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
8000f12: 687b ldr r3, [r7, #4]
8000f14: 6a5b ldr r3, [r3, #36] ; 0x24
8000f16: f443 2200 orr.w r2, r3, #524288 ; 0x80000
8000f1a: 687b ldr r3, [r7, #4]
8000f1c: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000f1e: 2301 movs r3, #1
}
}
8000f20: 4618 mov r0, r3
8000f22: 3710 adds r7, #16
8000f24: 46bd mov sp, r7
8000f26: bd80 pop {r7, pc}
08000f28 <HAL_CAN_AddTxMessage>:
* the TxMailbox used to store the Tx message.
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
{
8000f28: b480 push {r7}
8000f2a: b089 sub sp, #36 ; 0x24
8000f2c: af00 add r7, sp, #0
8000f2e: 60f8 str r0, [r7, #12]
8000f30: 60b9 str r1, [r7, #8]
8000f32: 607a str r2, [r7, #4]
8000f34: 603b str r3, [r7, #0]
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
8000f36: 68fb ldr r3, [r7, #12]
8000f38: f893 3020 ldrb.w r3, [r3, #32]
8000f3c: 77fb strb r3, [r7, #31]
uint32_t tsr = READ_REG(hcan->Instance->TSR);
8000f3e: 68fb ldr r3, [r7, #12]
8000f40: 681b ldr r3, [r3, #0]
8000f42: 689b ldr r3, [r3, #8]
8000f44: 61bb str r3, [r7, #24]
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
8000f46: 7ffb ldrb r3, [r7, #31]
8000f48: 2b01 cmp r3, #1
8000f4a: d003 beq.n 8000f54 <HAL_CAN_AddTxMessage+0x2c>
8000f4c: 7ffb ldrb r3, [r7, #31]
8000f4e: 2b02 cmp r3, #2
8000f50: f040 80b8 bne.w 80010c4 <HAL_CAN_AddTxMessage+0x19c>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
8000f54: 69bb ldr r3, [r7, #24]
8000f56: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8000f5a: 2b00 cmp r3, #0
8000f5c: d10a bne.n 8000f74 <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME1) != 0U) ||
8000f5e: 69bb ldr r3, [r7, #24]
8000f60: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
if (((tsr & CAN_TSR_TME0) != 0U) ||
8000f64: 2b00 cmp r3, #0
8000f66: d105 bne.n 8000f74 <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME2) != 0U))
8000f68: 69bb ldr r3, [r7, #24]
8000f6a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
((tsr & CAN_TSR_TME1) != 0U) ||
8000f6e: 2b00 cmp r3, #0
8000f70: f000 80a0 beq.w 80010b4 <HAL_CAN_AddTxMessage+0x18c>
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
8000f74: 69bb ldr r3, [r7, #24]
8000f76: 0e1b lsrs r3, r3, #24
8000f78: f003 0303 and.w r3, r3, #3
8000f7c: 617b str r3, [r7, #20]
/* Check transmit mailbox value */
if (transmitmailbox > 2U)
8000f7e: 697b ldr r3, [r7, #20]
8000f80: 2b02 cmp r3, #2
8000f82: d907 bls.n 8000f94 <HAL_CAN_AddTxMessage+0x6c>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
8000f84: 68fb ldr r3, [r7, #12]
8000f86: 6a5b ldr r3, [r3, #36] ; 0x24
8000f88: f443 0200 orr.w r2, r3, #8388608 ; 0x800000
8000f8c: 68fb ldr r3, [r7, #12]
8000f8e: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000f90: 2301 movs r3, #1
8000f92: e09e b.n 80010d2 <HAL_CAN_AddTxMessage+0x1aa>
}
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
8000f94: 2201 movs r2, #1
8000f96: 697b ldr r3, [r7, #20]
8000f98: 409a lsls r2, r3
8000f9a: 683b ldr r3, [r7, #0]
8000f9c: 601a str r2, [r3, #0]
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
8000f9e: 68bb ldr r3, [r7, #8]
8000fa0: 689b ldr r3, [r3, #8]
8000fa2: 2b00 cmp r3, #0
8000fa4: d10d bne.n 8000fc2 <HAL_CAN_AddTxMessage+0x9a>
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8000fa6: 68bb ldr r3, [r7, #8]
8000fa8: 681b ldr r3, [r3, #0]
8000faa: 055a lsls r2, r3, #21
pHeader->RTR);
8000fac: 68bb ldr r3, [r7, #8]
8000fae: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8000fb0: 68f9 ldr r1, [r7, #12]
8000fb2: 6809 ldr r1, [r1, #0]
8000fb4: 431a orrs r2, r3
8000fb6: 697b ldr r3, [r7, #20]
8000fb8: 3318 adds r3, #24
8000fba: 011b lsls r3, r3, #4
8000fbc: 440b add r3, r1
8000fbe: 601a str r2, [r3, #0]
8000fc0: e00f b.n 8000fe2 <HAL_CAN_AddTxMessage+0xba>
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8000fc2: 68bb ldr r3, [r7, #8]
8000fc4: 685b ldr r3, [r3, #4]
8000fc6: 00da lsls r2, r3, #3
pHeader->IDE |
8000fc8: 68bb ldr r3, [r7, #8]
8000fca: 689b ldr r3, [r3, #8]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8000fcc: 431a orrs r2, r3
pHeader->RTR);
8000fce: 68bb ldr r3, [r7, #8]
8000fd0: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8000fd2: 68f9 ldr r1, [r7, #12]
8000fd4: 6809 ldr r1, [r1, #0]
pHeader->IDE |
8000fd6: 431a orrs r2, r3
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8000fd8: 697b ldr r3, [r7, #20]
8000fda: 3318 adds r3, #24
8000fdc: 011b lsls r3, r3, #4
8000fde: 440b add r3, r1
8000fe0: 601a str r2, [r3, #0]
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
8000fe2: 68fb ldr r3, [r7, #12]
8000fe4: 6819 ldr r1, [r3, #0]
8000fe6: 68bb ldr r3, [r7, #8]
8000fe8: 691a ldr r2, [r3, #16]
8000fea: 697b ldr r3, [r7, #20]
8000fec: 3318 adds r3, #24
8000fee: 011b lsls r3, r3, #4
8000ff0: 440b add r3, r1
8000ff2: 3304 adds r3, #4
8000ff4: 601a str r2, [r3, #0]
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
8000ff6: 68bb ldr r3, [r7, #8]
8000ff8: 7d1b ldrb r3, [r3, #20]
8000ffa: 2b01 cmp r3, #1
8000ffc: d111 bne.n 8001022 <HAL_CAN_AddTxMessage+0xfa>
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
8000ffe: 68fb ldr r3, [r7, #12]
8001000: 681a ldr r2, [r3, #0]
8001002: 697b ldr r3, [r7, #20]
8001004: 3318 adds r3, #24
8001006: 011b lsls r3, r3, #4
8001008: 4413 add r3, r2
800100a: 3304 adds r3, #4
800100c: 681b ldr r3, [r3, #0]
800100e: 68fa ldr r2, [r7, #12]
8001010: 6811 ldr r1, [r2, #0]
8001012: f443 7280 orr.w r2, r3, #256 ; 0x100
8001016: 697b ldr r3, [r7, #20]
8001018: 3318 adds r3, #24
800101a: 011b lsls r3, r3, #4
800101c: 440b add r3, r1
800101e: 3304 adds r3, #4
8001020: 601a str r2, [r3, #0]
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
8001022: 687b ldr r3, [r7, #4]
8001024: 3307 adds r3, #7
8001026: 781b ldrb r3, [r3, #0]
8001028: 061a lsls r2, r3, #24
800102a: 687b ldr r3, [r7, #4]
800102c: 3306 adds r3, #6
800102e: 781b ldrb r3, [r3, #0]
8001030: 041b lsls r3, r3, #16
8001032: 431a orrs r2, r3
8001034: 687b ldr r3, [r7, #4]
8001036: 3305 adds r3, #5
8001038: 781b ldrb r3, [r3, #0]
800103a: 021b lsls r3, r3, #8
800103c: 4313 orrs r3, r2
800103e: 687a ldr r2, [r7, #4]
8001040: 3204 adds r2, #4
8001042: 7812 ldrb r2, [r2, #0]
8001044: 4610 mov r0, r2
8001046: 68fa ldr r2, [r7, #12]
8001048: 6811 ldr r1, [r2, #0]
800104a: ea43 0200 orr.w r2, r3, r0
800104e: 697b ldr r3, [r7, #20]
8001050: 011b lsls r3, r3, #4
8001052: 440b add r3, r1
8001054: f503 73c6 add.w r3, r3, #396 ; 0x18c
8001058: 601a str r2, [r3, #0]
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
800105a: 687b ldr r3, [r7, #4]
800105c: 3303 adds r3, #3
800105e: 781b ldrb r3, [r3, #0]
8001060: 061a lsls r2, r3, #24
8001062: 687b ldr r3, [r7, #4]
8001064: 3302 adds r3, #2
8001066: 781b ldrb r3, [r3, #0]
8001068: 041b lsls r3, r3, #16
800106a: 431a orrs r2, r3
800106c: 687b ldr r3, [r7, #4]
800106e: 3301 adds r3, #1
8001070: 781b ldrb r3, [r3, #0]
8001072: 021b lsls r3, r3, #8
8001074: 4313 orrs r3, r2
8001076: 687a ldr r2, [r7, #4]
8001078: 7812 ldrb r2, [r2, #0]
800107a: 4610 mov r0, r2
800107c: 68fa ldr r2, [r7, #12]
800107e: 6811 ldr r1, [r2, #0]
8001080: ea43 0200 orr.w r2, r3, r0
8001084: 697b ldr r3, [r7, #20]
8001086: 011b lsls r3, r3, #4
8001088: 440b add r3, r1
800108a: f503 73c4 add.w r3, r3, #392 ; 0x188
800108e: 601a str r2, [r3, #0]
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
8001090: 68fb ldr r3, [r7, #12]
8001092: 681a ldr r2, [r3, #0]
8001094: 697b ldr r3, [r7, #20]
8001096: 3318 adds r3, #24
8001098: 011b lsls r3, r3, #4
800109a: 4413 add r3, r2
800109c: 681b ldr r3, [r3, #0]
800109e: 68fa ldr r2, [r7, #12]
80010a0: 6811 ldr r1, [r2, #0]
80010a2: f043 0201 orr.w r2, r3, #1
80010a6: 697b ldr r3, [r7, #20]
80010a8: 3318 adds r3, #24
80010aa: 011b lsls r3, r3, #4
80010ac: 440b add r3, r1
80010ae: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
80010b0: 2300 movs r3, #0
80010b2: e00e b.n 80010d2 <HAL_CAN_AddTxMessage+0x1aa>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80010b4: 68fb ldr r3, [r7, #12]
80010b6: 6a5b ldr r3, [r3, #36] ; 0x24
80010b8: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
80010bc: 68fb ldr r3, [r7, #12]
80010be: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80010c0: 2301 movs r3, #1
80010c2: e006 b.n 80010d2 <HAL_CAN_AddTxMessage+0x1aa>
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
80010c4: 68fb ldr r3, [r7, #12]
80010c6: 6a5b ldr r3, [r3, #36] ; 0x24
80010c8: f443 2280 orr.w r2, r3, #262144 ; 0x40000
80010cc: 68fb ldr r3, [r7, #12]
80010ce: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80010d0: 2301 movs r3, #1
}
}
80010d2: 4618 mov r0, r3
80010d4: 3724 adds r7, #36 ; 0x24
80010d6: 46bd mov sp, r7
80010d8: f85d 7b04 ldr.w r7, [sp], #4
80010dc: 4770 bx lr
080010de <HAL_CAN_GetRxMessage>:
* of the Rx frame will be stored.
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
80010de: b480 push {r7}
80010e0: b087 sub sp, #28
80010e2: af00 add r7, sp, #0
80010e4: 60f8 str r0, [r7, #12]
80010e6: 60b9 str r1, [r7, #8]
80010e8: 607a str r2, [r7, #4]
80010ea: 603b str r3, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
80010ec: 68fb ldr r3, [r7, #12]
80010ee: f893 3020 ldrb.w r3, [r3, #32]
80010f2: 75fb strb r3, [r7, #23]
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
80010f4: 7dfb ldrb r3, [r7, #23]
80010f6: 2b01 cmp r3, #1
80010f8: d003 beq.n 8001102 <HAL_CAN_GetRxMessage+0x24>
80010fa: 7dfb ldrb r3, [r7, #23]
80010fc: 2b02 cmp r3, #2
80010fe: f040 80f3 bne.w 80012e8 <HAL_CAN_GetRxMessage+0x20a>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
8001102: 68bb ldr r3, [r7, #8]
8001104: 2b00 cmp r3, #0
8001106: d10e bne.n 8001126 <HAL_CAN_GetRxMessage+0x48>
{
/* Check that the Rx FIFO 0 is not empty */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
8001108: 68fb ldr r3, [r7, #12]
800110a: 681b ldr r3, [r3, #0]
800110c: 68db ldr r3, [r3, #12]
800110e: f003 0303 and.w r3, r3, #3
8001112: 2b00 cmp r3, #0
8001114: d116 bne.n 8001144 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8001116: 68fb ldr r3, [r7, #12]
8001118: 6a5b ldr r3, [r3, #36] ; 0x24
800111a: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
800111e: 68fb ldr r3, [r7, #12]
8001120: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8001122: 2301 movs r3, #1
8001124: e0e7 b.n 80012f6 <HAL_CAN_GetRxMessage+0x218>
}
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
8001126: 68fb ldr r3, [r7, #12]
8001128: 681b ldr r3, [r3, #0]
800112a: 691b ldr r3, [r3, #16]
800112c: f003 0303 and.w r3, r3, #3
8001130: 2b00 cmp r3, #0
8001132: d107 bne.n 8001144 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8001134: 68fb ldr r3, [r7, #12]
8001136: 6a5b ldr r3, [r3, #36] ; 0x24
8001138: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
800113c: 68fb ldr r3, [r7, #12]
800113e: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8001140: 2301 movs r3, #1
8001142: e0d8 b.n 80012f6 <HAL_CAN_GetRxMessage+0x218>
}
}
/* Get the header */
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
8001144: 68fb ldr r3, [r7, #12]
8001146: 681a ldr r2, [r3, #0]
8001148: 68bb ldr r3, [r7, #8]
800114a: 331b adds r3, #27
800114c: 011b lsls r3, r3, #4
800114e: 4413 add r3, r2
8001150: 681b ldr r3, [r3, #0]
8001152: f003 0204 and.w r2, r3, #4
8001156: 687b ldr r3, [r7, #4]
8001158: 609a str r2, [r3, #8]
if (pHeader->IDE == CAN_ID_STD)
800115a: 687b ldr r3, [r7, #4]
800115c: 689b ldr r3, [r3, #8]
800115e: 2b00 cmp r3, #0
8001160: d10c bne.n 800117c <HAL_CAN_GetRxMessage+0x9e>
{
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
8001162: 68fb ldr r3, [r7, #12]
8001164: 681a ldr r2, [r3, #0]
8001166: 68bb ldr r3, [r7, #8]
8001168: 331b adds r3, #27
800116a: 011b lsls r3, r3, #4
800116c: 4413 add r3, r2
800116e: 681b ldr r3, [r3, #0]
8001170: 0d5b lsrs r3, r3, #21
8001172: f3c3 020a ubfx r2, r3, #0, #11
8001176: 687b ldr r3, [r7, #4]
8001178: 601a str r2, [r3, #0]
800117a: e00b b.n 8001194 <HAL_CAN_GetRxMessage+0xb6>
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
800117c: 68fb ldr r3, [r7, #12]
800117e: 681a ldr r2, [r3, #0]
8001180: 68bb ldr r3, [r7, #8]
8001182: 331b adds r3, #27
8001184: 011b lsls r3, r3, #4
8001186: 4413 add r3, r2
8001188: 681b ldr r3, [r3, #0]
800118a: 08db lsrs r3, r3, #3
800118c: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000
8001190: 687b ldr r3, [r7, #4]
8001192: 605a str r2, [r3, #4]
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
8001194: 68fb ldr r3, [r7, #12]
8001196: 681a ldr r2, [r3, #0]
8001198: 68bb ldr r3, [r7, #8]
800119a: 331b adds r3, #27
800119c: 011b lsls r3, r3, #4
800119e: 4413 add r3, r2
80011a0: 681b ldr r3, [r3, #0]
80011a2: f003 0202 and.w r2, r3, #2
80011a6: 687b ldr r3, [r7, #4]
80011a8: 60da str r2, [r3, #12]
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
80011aa: 68fb ldr r3, [r7, #12]
80011ac: 681a ldr r2, [r3, #0]
80011ae: 68bb ldr r3, [r7, #8]
80011b0: 331b adds r3, #27
80011b2: 011b lsls r3, r3, #4
80011b4: 4413 add r3, r2
80011b6: 3304 adds r3, #4
80011b8: 681b ldr r3, [r3, #0]
80011ba: f003 020f and.w r2, r3, #15
80011be: 687b ldr r3, [r7, #4]
80011c0: 611a str r2, [r3, #16]
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
80011c2: 68fb ldr r3, [r7, #12]
80011c4: 681a ldr r2, [r3, #0]
80011c6: 68bb ldr r3, [r7, #8]
80011c8: 331b adds r3, #27
80011ca: 011b lsls r3, r3, #4
80011cc: 4413 add r3, r2
80011ce: 3304 adds r3, #4
80011d0: 681b ldr r3, [r3, #0]
80011d2: 0a1b lsrs r3, r3, #8
80011d4: b2da uxtb r2, r3
80011d6: 687b ldr r3, [r7, #4]
80011d8: 619a str r2, [r3, #24]
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
80011da: 68fb ldr r3, [r7, #12]
80011dc: 681a ldr r2, [r3, #0]
80011de: 68bb ldr r3, [r7, #8]
80011e0: 331b adds r3, #27
80011e2: 011b lsls r3, r3, #4
80011e4: 4413 add r3, r2
80011e6: 3304 adds r3, #4
80011e8: 681b ldr r3, [r3, #0]
80011ea: 0c1b lsrs r3, r3, #16
80011ec: b29a uxth r2, r3
80011ee: 687b ldr r3, [r7, #4]
80011f0: 615a str r2, [r3, #20]
/* Get the data */
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
80011f2: 68fb ldr r3, [r7, #12]
80011f4: 681a ldr r2, [r3, #0]
80011f6: 68bb ldr r3, [r7, #8]
80011f8: 011b lsls r3, r3, #4
80011fa: 4413 add r3, r2
80011fc: f503 73dc add.w r3, r3, #440 ; 0x1b8
8001200: 681b ldr r3, [r3, #0]
8001202: b2da uxtb r2, r3
8001204: 683b ldr r3, [r7, #0]
8001206: 701a strb r2, [r3, #0]
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
8001208: 68fb ldr r3, [r7, #12]
800120a: 681a ldr r2, [r3, #0]
800120c: 68bb ldr r3, [r7, #8]
800120e: 011b lsls r3, r3, #4
8001210: 4413 add r3, r2
8001212: f503 73dc add.w r3, r3, #440 ; 0x1b8
8001216: 681b ldr r3, [r3, #0]
8001218: 0a1a lsrs r2, r3, #8
800121a: 683b ldr r3, [r7, #0]
800121c: 3301 adds r3, #1
800121e: b2d2 uxtb r2, r2
8001220: 701a strb r2, [r3, #0]
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
8001222: 68fb ldr r3, [r7, #12]
8001224: 681a ldr r2, [r3, #0]
8001226: 68bb ldr r3, [r7, #8]
8001228: 011b lsls r3, r3, #4
800122a: 4413 add r3, r2
800122c: f503 73dc add.w r3, r3, #440 ; 0x1b8
8001230: 681b ldr r3, [r3, #0]
8001232: 0c1a lsrs r2, r3, #16
8001234: 683b ldr r3, [r7, #0]
8001236: 3302 adds r3, #2
8001238: b2d2 uxtb r2, r2
800123a: 701a strb r2, [r3, #0]
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
800123c: 68fb ldr r3, [r7, #12]
800123e: 681a ldr r2, [r3, #0]
8001240: 68bb ldr r3, [r7, #8]
8001242: 011b lsls r3, r3, #4
8001244: 4413 add r3, r2
8001246: f503 73dc add.w r3, r3, #440 ; 0x1b8
800124a: 681b ldr r3, [r3, #0]
800124c: 0e1a lsrs r2, r3, #24
800124e: 683b ldr r3, [r7, #0]
8001250: 3303 adds r3, #3
8001252: b2d2 uxtb r2, r2
8001254: 701a strb r2, [r3, #0]
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
8001256: 68fb ldr r3, [r7, #12]
8001258: 681a ldr r2, [r3, #0]
800125a: 68bb ldr r3, [r7, #8]
800125c: 011b lsls r3, r3, #4
800125e: 4413 add r3, r2
8001260: f503 73de add.w r3, r3, #444 ; 0x1bc
8001264: 681a ldr r2, [r3, #0]
8001266: 683b ldr r3, [r7, #0]
8001268: 3304 adds r3, #4
800126a: b2d2 uxtb r2, r2
800126c: 701a strb r2, [r3, #0]
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
800126e: 68fb ldr r3, [r7, #12]
8001270: 681a ldr r2, [r3, #0]
8001272: 68bb ldr r3, [r7, #8]
8001274: 011b lsls r3, r3, #4
8001276: 4413 add r3, r2
8001278: f503 73de add.w r3, r3, #444 ; 0x1bc
800127c: 681b ldr r3, [r3, #0]
800127e: 0a1a lsrs r2, r3, #8
8001280: 683b ldr r3, [r7, #0]
8001282: 3305 adds r3, #5
8001284: b2d2 uxtb r2, r2
8001286: 701a strb r2, [r3, #0]
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
8001288: 68fb ldr r3, [r7, #12]
800128a: 681a ldr r2, [r3, #0]
800128c: 68bb ldr r3, [r7, #8]
800128e: 011b lsls r3, r3, #4
8001290: 4413 add r3, r2
8001292: f503 73de add.w r3, r3, #444 ; 0x1bc
8001296: 681b ldr r3, [r3, #0]
8001298: 0c1a lsrs r2, r3, #16
800129a: 683b ldr r3, [r7, #0]
800129c: 3306 adds r3, #6
800129e: b2d2 uxtb r2, r2
80012a0: 701a strb r2, [r3, #0]
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
80012a2: 68fb ldr r3, [r7, #12]
80012a4: 681a ldr r2, [r3, #0]
80012a6: 68bb ldr r3, [r7, #8]
80012a8: 011b lsls r3, r3, #4
80012aa: 4413 add r3, r2
80012ac: f503 73de add.w r3, r3, #444 ; 0x1bc
80012b0: 681b ldr r3, [r3, #0]
80012b2: 0e1a lsrs r2, r3, #24
80012b4: 683b ldr r3, [r7, #0]
80012b6: 3307 adds r3, #7
80012b8: b2d2 uxtb r2, r2
80012ba: 701a strb r2, [r3, #0]
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
80012bc: 68bb ldr r3, [r7, #8]
80012be: 2b00 cmp r3, #0
80012c0: d108 bne.n 80012d4 <HAL_CAN_GetRxMessage+0x1f6>
{
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
80012c2: 68fb ldr r3, [r7, #12]
80012c4: 681b ldr r3, [r3, #0]
80012c6: 68da ldr r2, [r3, #12]
80012c8: 68fb ldr r3, [r7, #12]
80012ca: 681b ldr r3, [r3, #0]
80012cc: f042 0220 orr.w r2, r2, #32
80012d0: 60da str r2, [r3, #12]
80012d2: e007 b.n 80012e4 <HAL_CAN_GetRxMessage+0x206>
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
80012d4: 68fb ldr r3, [r7, #12]
80012d6: 681b ldr r3, [r3, #0]
80012d8: 691a ldr r2, [r3, #16]
80012da: 68fb ldr r3, [r7, #12]
80012dc: 681b ldr r3, [r3, #0]
80012de: f042 0220 orr.w r2, r2, #32
80012e2: 611a str r2, [r3, #16]
}
/* Return function status */
return HAL_OK;
80012e4: 2300 movs r3, #0
80012e6: e006 b.n 80012f6 <HAL_CAN_GetRxMessage+0x218>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
80012e8: 68fb ldr r3, [r7, #12]
80012ea: 6a5b ldr r3, [r3, #36] ; 0x24
80012ec: f443 2280 orr.w r2, r3, #262144 ; 0x40000
80012f0: 68fb ldr r3, [r7, #12]
80012f2: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80012f4: 2301 movs r3, #1
}
}
80012f6: 4618 mov r0, r3
80012f8: 371c adds r7, #28
80012fa: 46bd mov sp, r7
80012fc: f85d 7b04 ldr.w r7, [sp], #4
8001300: 4770 bx lr
08001302 <HAL_CAN_GetRxFifoFillLevel>:
* @param RxFifo Rx FIFO.
* This parameter can be a value of @arg CAN_receive_FIFO_number.
* @retval Number of messages available in Rx FIFO.
*/
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
{
8001302: b480 push {r7}
8001304: b085 sub sp, #20
8001306: af00 add r7, sp, #0
8001308: 6078 str r0, [r7, #4]
800130a: 6039 str r1, [r7, #0]
uint32_t filllevel = 0U;
800130c: 2300 movs r3, #0
800130e: 60fb str r3, [r7, #12]
HAL_CAN_StateTypeDef state = hcan->State;
8001310: 687b ldr r3, [r7, #4]
8001312: f893 3020 ldrb.w r3, [r3, #32]
8001316: 72fb strb r3, [r7, #11]
/* Check function parameters */
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
8001318: 7afb ldrb r3, [r7, #11]
800131a: 2b01 cmp r3, #1
800131c: d002 beq.n 8001324 <HAL_CAN_GetRxFifoFillLevel+0x22>
800131e: 7afb ldrb r3, [r7, #11]
8001320: 2b02 cmp r3, #2
8001322: d10f bne.n 8001344 <HAL_CAN_GetRxFifoFillLevel+0x42>
(state == HAL_CAN_STATE_LISTENING))
{
if (RxFifo == CAN_RX_FIFO0)
8001324: 683b ldr r3, [r7, #0]
8001326: 2b00 cmp r3, #0
8001328: d106 bne.n 8001338 <HAL_CAN_GetRxFifoFillLevel+0x36>
{
filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
800132a: 687b ldr r3, [r7, #4]
800132c: 681b ldr r3, [r3, #0]
800132e: 68db ldr r3, [r3, #12]
8001330: f003 0303 and.w r3, r3, #3
8001334: 60fb str r3, [r7, #12]
8001336: e005 b.n 8001344 <HAL_CAN_GetRxFifoFillLevel+0x42>
}
else /* RxFifo == CAN_RX_FIFO1 */
{
filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
8001338: 687b ldr r3, [r7, #4]
800133a: 681b ldr r3, [r3, #0]
800133c: 691b ldr r3, [r3, #16]
800133e: f003 0303 and.w r3, r3, #3
8001342: 60fb str r3, [r7, #12]
}
}
/* Return Rx FIFO fill level */
return filllevel;
8001344: 68fb ldr r3, [r7, #12]
}
8001346: 4618 mov r0, r3
8001348: 3714 adds r7, #20
800134a: 46bd mov sp, r7
800134c: f85d 7b04 ldr.w r7, [sp], #4
8001350: 4770 bx lr
...
08001354 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001354: b480 push {r7}
8001356: b085 sub sp, #20
8001358: af00 add r7, sp, #0
800135a: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
800135c: 687b ldr r3, [r7, #4]
800135e: f003 0307 and.w r3, r3, #7
8001362: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001364: 4b0c ldr r3, [pc, #48] ; (8001398 <__NVIC_SetPriorityGrouping+0x44>)
8001366: 68db ldr r3, [r3, #12]
8001368: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
800136a: 68ba ldr r2, [r7, #8]
800136c: f64f 03ff movw r3, #63743 ; 0xf8ff
8001370: 4013 ands r3, r2
8001372: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001374: 68fb ldr r3, [r7, #12]
8001376: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001378: 68bb ldr r3, [r7, #8]
800137a: 4313 orrs r3, r2
reg_value = (reg_value |
800137c: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8001380: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001384: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8001386: 4a04 ldr r2, [pc, #16] ; (8001398 <__NVIC_SetPriorityGrouping+0x44>)
8001388: 68bb ldr r3, [r7, #8]
800138a: 60d3 str r3, [r2, #12]
}
800138c: bf00 nop
800138e: 3714 adds r7, #20
8001390: 46bd mov sp, r7
8001392: f85d 7b04 ldr.w r7, [sp], #4
8001396: 4770 bx lr
8001398: e000ed00 .word 0xe000ed00
0800139c <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
800139c: b480 push {r7}
800139e: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
80013a0: 4b04 ldr r3, [pc, #16] ; (80013b4 <__NVIC_GetPriorityGrouping+0x18>)
80013a2: 68db ldr r3, [r3, #12]
80013a4: 0a1b lsrs r3, r3, #8
80013a6: f003 0307 and.w r3, r3, #7
}
80013aa: 4618 mov r0, r3
80013ac: 46bd mov sp, r7
80013ae: f85d 7b04 ldr.w r7, [sp], #4
80013b2: 4770 bx lr
80013b4: e000ed00 .word 0xe000ed00
080013b8 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80013b8: b480 push {r7}
80013ba: b083 sub sp, #12
80013bc: af00 add r7, sp, #0
80013be: 4603 mov r3, r0
80013c0: 6039 str r1, [r7, #0]
80013c2: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80013c4: f997 3007 ldrsb.w r3, [r7, #7]
80013c8: 2b00 cmp r3, #0
80013ca: db0a blt.n 80013e2 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80013cc: 683b ldr r3, [r7, #0]
80013ce: b2da uxtb r2, r3
80013d0: 490c ldr r1, [pc, #48] ; (8001404 <__NVIC_SetPriority+0x4c>)
80013d2: f997 3007 ldrsb.w r3, [r7, #7]
80013d6: 0112 lsls r2, r2, #4
80013d8: b2d2 uxtb r2, r2
80013da: 440b add r3, r1
80013dc: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
80013e0: e00a b.n 80013f8 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80013e2: 683b ldr r3, [r7, #0]
80013e4: b2da uxtb r2, r3
80013e6: 4908 ldr r1, [pc, #32] ; (8001408 <__NVIC_SetPriority+0x50>)
80013e8: 79fb ldrb r3, [r7, #7]
80013ea: f003 030f and.w r3, r3, #15
80013ee: 3b04 subs r3, #4
80013f0: 0112 lsls r2, r2, #4
80013f2: b2d2 uxtb r2, r2
80013f4: 440b add r3, r1
80013f6: 761a strb r2, [r3, #24]
}
80013f8: bf00 nop
80013fa: 370c adds r7, #12
80013fc: 46bd mov sp, r7
80013fe: f85d 7b04 ldr.w r7, [sp], #4
8001402: 4770 bx lr
8001404: e000e100 .word 0xe000e100
8001408: e000ed00 .word 0xe000ed00
0800140c <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
800140c: b480 push {r7}
800140e: b089 sub sp, #36 ; 0x24
8001410: af00 add r7, sp, #0
8001412: 60f8 str r0, [r7, #12]
8001414: 60b9 str r1, [r7, #8]
8001416: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001418: 68fb ldr r3, [r7, #12]
800141a: f003 0307 and.w r3, r3, #7
800141e: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001420: 69fb ldr r3, [r7, #28]
8001422: f1c3 0307 rsb r3, r3, #7
8001426: 2b04 cmp r3, #4
8001428: bf28 it cs
800142a: 2304 movcs r3, #4
800142c: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
800142e: 69fb ldr r3, [r7, #28]
8001430: 3304 adds r3, #4
8001432: 2b06 cmp r3, #6
8001434: d902 bls.n 800143c <NVIC_EncodePriority+0x30>
8001436: 69fb ldr r3, [r7, #28]
8001438: 3b03 subs r3, #3
800143a: e000 b.n 800143e <NVIC_EncodePriority+0x32>
800143c: 2300 movs r3, #0
800143e: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001440: f04f 32ff mov.w r2, #4294967295
8001444: 69bb ldr r3, [r7, #24]
8001446: fa02 f303 lsl.w r3, r2, r3
800144a: 43da mvns r2, r3
800144c: 68bb ldr r3, [r7, #8]
800144e: 401a ands r2, r3
8001450: 697b ldr r3, [r7, #20]
8001452: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8001454: f04f 31ff mov.w r1, #4294967295
8001458: 697b ldr r3, [r7, #20]
800145a: fa01 f303 lsl.w r3, r1, r3
800145e: 43d9 mvns r1, r3
8001460: 687b ldr r3, [r7, #4]
8001462: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001464: 4313 orrs r3, r2
);
}
8001466: 4618 mov r0, r3
8001468: 3724 adds r7, #36 ; 0x24
800146a: 46bd mov sp, r7
800146c: f85d 7b04 ldr.w r7, [sp], #4
8001470: 4770 bx lr
...
08001474 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8001474: b580 push {r7, lr}
8001476: b082 sub sp, #8
8001478: af00 add r7, sp, #0
800147a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
800147c: 687b ldr r3, [r7, #4]
800147e: 3b01 subs r3, #1
8001480: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8001484: d301 bcc.n 800148a <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8001486: 2301 movs r3, #1
8001488: e00f b.n 80014aa <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
800148a: 4a0a ldr r2, [pc, #40] ; (80014b4 <SysTick_Config+0x40>)
800148c: 687b ldr r3, [r7, #4]
800148e: 3b01 subs r3, #1
8001490: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8001492: 210f movs r1, #15
8001494: f04f 30ff mov.w r0, #4294967295
8001498: f7ff ff8e bl 80013b8 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
800149c: 4b05 ldr r3, [pc, #20] ; (80014b4 <SysTick_Config+0x40>)
800149e: 2200 movs r2, #0
80014a0: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80014a2: 4b04 ldr r3, [pc, #16] ; (80014b4 <SysTick_Config+0x40>)
80014a4: 2207 movs r2, #7
80014a6: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80014a8: 2300 movs r3, #0
}
80014aa: 4618 mov r0, r3
80014ac: 3708 adds r7, #8
80014ae: 46bd mov sp, r7
80014b0: bd80 pop {r7, pc}
80014b2: bf00 nop
80014b4: e000e010 .word 0xe000e010
080014b8 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80014b8: b580 push {r7, lr}
80014ba: b082 sub sp, #8
80014bc: af00 add r7, sp, #0
80014be: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
80014c0: 6878 ldr r0, [r7, #4]
80014c2: f7ff ff47 bl 8001354 <__NVIC_SetPriorityGrouping>
}
80014c6: bf00 nop
80014c8: 3708 adds r7, #8
80014ca: 46bd mov sp, r7
80014cc: bd80 pop {r7, pc}
080014ce <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
80014ce: b580 push {r7, lr}
80014d0: b086 sub sp, #24
80014d2: af00 add r7, sp, #0
80014d4: 4603 mov r3, r0
80014d6: 60b9 str r1, [r7, #8]
80014d8: 607a str r2, [r7, #4]
80014da: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
80014dc: 2300 movs r3, #0
80014de: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
80014e0: f7ff ff5c bl 800139c <__NVIC_GetPriorityGrouping>
80014e4: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
80014e6: 687a ldr r2, [r7, #4]
80014e8: 68b9 ldr r1, [r7, #8]
80014ea: 6978 ldr r0, [r7, #20]
80014ec: f7ff ff8e bl 800140c <NVIC_EncodePriority>
80014f0: 4602 mov r2, r0
80014f2: f997 300f ldrsb.w r3, [r7, #15]
80014f6: 4611 mov r1, r2
80014f8: 4618 mov r0, r3
80014fa: f7ff ff5d bl 80013b8 <__NVIC_SetPriority>
}
80014fe: bf00 nop
8001500: 3718 adds r7, #24
8001502: 46bd mov sp, r7
8001504: bd80 pop {r7, pc}
08001506 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8001506: b580 push {r7, lr}
8001508: b082 sub sp, #8
800150a: af00 add r7, sp, #0
800150c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
800150e: 6878 ldr r0, [r7, #4]
8001510: f7ff ffb0 bl 8001474 <SysTick_Config>
8001514: 4603 mov r3, r0
}
8001516: 4618 mov r0, r3
8001518: 3708 adds r7, #8
800151a: 46bd mov sp, r7
800151c: bd80 pop {r7, pc}
...
08001520 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001520: b480 push {r7}
8001522: b089 sub sp, #36 ; 0x24
8001524: af00 add r7, sp, #0
8001526: 6078 str r0, [r7, #4]
8001528: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
800152a: 2300 movs r3, #0
800152c: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
800152e: 2300 movs r3, #0
8001530: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8001532: 2300 movs r3, #0
8001534: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8001536: 2300 movs r3, #0
8001538: 61fb str r3, [r7, #28]
800153a: e16b b.n 8001814 <HAL_GPIO_Init+0x2f4>
{
/* Get the IO position */
ioposition = 0x01U << position;
800153c: 2201 movs r2, #1
800153e: 69fb ldr r3, [r7, #28]
8001540: fa02 f303 lsl.w r3, r2, r3
8001544: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8001546: 683b ldr r3, [r7, #0]
8001548: 681b ldr r3, [r3, #0]
800154a: 697a ldr r2, [r7, #20]
800154c: 4013 ands r3, r2
800154e: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8001550: 693a ldr r2, [r7, #16]
8001552: 697b ldr r3, [r7, #20]
8001554: 429a cmp r2, r3
8001556: f040 815a bne.w 800180e <HAL_GPIO_Init+0x2ee>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
800155a: 683b ldr r3, [r7, #0]
800155c: 685b ldr r3, [r3, #4]
800155e: f003 0303 and.w r3, r3, #3
8001562: 2b01 cmp r3, #1
8001564: d005 beq.n 8001572 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001566: 683b ldr r3, [r7, #0]
8001568: 685b ldr r3, [r3, #4]
800156a: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
800156e: 2b02 cmp r3, #2
8001570: d130 bne.n 80015d4 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001572: 687b ldr r3, [r7, #4]
8001574: 689b ldr r3, [r3, #8]
8001576: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8001578: 69fb ldr r3, [r7, #28]
800157a: 005b lsls r3, r3, #1
800157c: 2203 movs r2, #3
800157e: fa02 f303 lsl.w r3, r2, r3
8001582: 43db mvns r3, r3
8001584: 69ba ldr r2, [r7, #24]
8001586: 4013 ands r3, r2
8001588: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
800158a: 683b ldr r3, [r7, #0]
800158c: 68da ldr r2, [r3, #12]
800158e: 69fb ldr r3, [r7, #28]
8001590: 005b lsls r3, r3, #1
8001592: fa02 f303 lsl.w r3, r2, r3
8001596: 69ba ldr r2, [r7, #24]
8001598: 4313 orrs r3, r2
800159a: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
800159c: 687b ldr r3, [r7, #4]
800159e: 69ba ldr r2, [r7, #24]
80015a0: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
80015a2: 687b ldr r3, [r7, #4]
80015a4: 685b ldr r3, [r3, #4]
80015a6: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
80015a8: 2201 movs r2, #1
80015aa: 69fb ldr r3, [r7, #28]
80015ac: fa02 f303 lsl.w r3, r2, r3
80015b0: 43db mvns r3, r3
80015b2: 69ba ldr r2, [r7, #24]
80015b4: 4013 ands r3, r2
80015b6: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80015b8: 683b ldr r3, [r7, #0]
80015ba: 685b ldr r3, [r3, #4]
80015bc: 091b lsrs r3, r3, #4
80015be: f003 0201 and.w r2, r3, #1
80015c2: 69fb ldr r3, [r7, #28]
80015c4: fa02 f303 lsl.w r3, r2, r3
80015c8: 69ba ldr r2, [r7, #24]
80015ca: 4313 orrs r3, r2
80015cc: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
80015ce: 687b ldr r3, [r7, #4]
80015d0: 69ba ldr r2, [r7, #24]
80015d2: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
80015d4: 683b ldr r3, [r7, #0]
80015d6: 685b ldr r3, [r3, #4]
80015d8: f003 0303 and.w r3, r3, #3
80015dc: 2b03 cmp r3, #3
80015de: d017 beq.n 8001610 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
80015e0: 687b ldr r3, [r7, #4]
80015e2: 68db ldr r3, [r3, #12]
80015e4: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
80015e6: 69fb ldr r3, [r7, #28]
80015e8: 005b lsls r3, r3, #1
80015ea: 2203 movs r2, #3
80015ec: fa02 f303 lsl.w r3, r2, r3
80015f0: 43db mvns r3, r3
80015f2: 69ba ldr r2, [r7, #24]
80015f4: 4013 ands r3, r2
80015f6: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
80015f8: 683b ldr r3, [r7, #0]
80015fa: 689a ldr r2, [r3, #8]
80015fc: 69fb ldr r3, [r7, #28]
80015fe: 005b lsls r3, r3, #1
8001600: fa02 f303 lsl.w r3, r2, r3
8001604: 69ba ldr r2, [r7, #24]
8001606: 4313 orrs r3, r2
8001608: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
800160a: 687b ldr r3, [r7, #4]
800160c: 69ba ldr r2, [r7, #24]
800160e: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001610: 683b ldr r3, [r7, #0]
8001612: 685b ldr r3, [r3, #4]
8001614: f003 0303 and.w r3, r3, #3
8001618: 2b02 cmp r3, #2
800161a: d123 bne.n 8001664 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
800161c: 69fb ldr r3, [r7, #28]
800161e: 08da lsrs r2, r3, #3
8001620: 687b ldr r3, [r7, #4]
8001622: 3208 adds r2, #8
8001624: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001628: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
800162a: 69fb ldr r3, [r7, #28]
800162c: f003 0307 and.w r3, r3, #7
8001630: 009b lsls r3, r3, #2
8001632: 220f movs r2, #15
8001634: fa02 f303 lsl.w r3, r2, r3
8001638: 43db mvns r3, r3
800163a: 69ba ldr r2, [r7, #24]
800163c: 4013 ands r3, r2
800163e: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8001640: 683b ldr r3, [r7, #0]
8001642: 691a ldr r2, [r3, #16]
8001644: 69fb ldr r3, [r7, #28]
8001646: f003 0307 and.w r3, r3, #7
800164a: 009b lsls r3, r3, #2
800164c: fa02 f303 lsl.w r3, r2, r3
8001650: 69ba ldr r2, [r7, #24]
8001652: 4313 orrs r3, r2
8001654: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8001656: 69fb ldr r3, [r7, #28]
8001658: 08da lsrs r2, r3, #3
800165a: 687b ldr r3, [r7, #4]
800165c: 3208 adds r2, #8
800165e: 69b9 ldr r1, [r7, #24]
8001660: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001664: 687b ldr r3, [r7, #4]
8001666: 681b ldr r3, [r3, #0]
8001668: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
800166a: 69fb ldr r3, [r7, #28]
800166c: 005b lsls r3, r3, #1
800166e: 2203 movs r2, #3
8001670: fa02 f303 lsl.w r3, r2, r3
8001674: 43db mvns r3, r3
8001676: 69ba ldr r2, [r7, #24]
8001678: 4013 ands r3, r2
800167a: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
800167c: 683b ldr r3, [r7, #0]
800167e: 685b ldr r3, [r3, #4]
8001680: f003 0203 and.w r2, r3, #3
8001684: 69fb ldr r3, [r7, #28]
8001686: 005b lsls r3, r3, #1
8001688: fa02 f303 lsl.w r3, r2, r3
800168c: 69ba ldr r2, [r7, #24]
800168e: 4313 orrs r3, r2
8001690: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8001692: 687b ldr r3, [r7, #4]
8001694: 69ba ldr r2, [r7, #24]
8001696: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8001698: 683b ldr r3, [r7, #0]
800169a: 685b ldr r3, [r3, #4]
800169c: f403 3340 and.w r3, r3, #196608 ; 0x30000
80016a0: 2b00 cmp r3, #0
80016a2: f000 80b4 beq.w 800180e <HAL_GPIO_Init+0x2ee>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80016a6: 2300 movs r3, #0
80016a8: 60fb str r3, [r7, #12]
80016aa: 4b60 ldr r3, [pc, #384] ; (800182c <HAL_GPIO_Init+0x30c>)
80016ac: 6c5b ldr r3, [r3, #68] ; 0x44
80016ae: 4a5f ldr r2, [pc, #380] ; (800182c <HAL_GPIO_Init+0x30c>)
80016b0: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80016b4: 6453 str r3, [r2, #68] ; 0x44
80016b6: 4b5d ldr r3, [pc, #372] ; (800182c <HAL_GPIO_Init+0x30c>)
80016b8: 6c5b ldr r3, [r3, #68] ; 0x44
80016ba: f403 4380 and.w r3, r3, #16384 ; 0x4000
80016be: 60fb str r3, [r7, #12]
80016c0: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
80016c2: 4a5b ldr r2, [pc, #364] ; (8001830 <HAL_GPIO_Init+0x310>)
80016c4: 69fb ldr r3, [r7, #28]
80016c6: 089b lsrs r3, r3, #2
80016c8: 3302 adds r3, #2
80016ca: f852 3023 ldr.w r3, [r2, r3, lsl #2]
80016ce: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
80016d0: 69fb ldr r3, [r7, #28]
80016d2: f003 0303 and.w r3, r3, #3
80016d6: 009b lsls r3, r3, #2
80016d8: 220f movs r2, #15
80016da: fa02 f303 lsl.w r3, r2, r3
80016de: 43db mvns r3, r3
80016e0: 69ba ldr r2, [r7, #24]
80016e2: 4013 ands r3, r2
80016e4: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
80016e6: 687b ldr r3, [r7, #4]
80016e8: 4a52 ldr r2, [pc, #328] ; (8001834 <HAL_GPIO_Init+0x314>)
80016ea: 4293 cmp r3, r2
80016ec: d02b beq.n 8001746 <HAL_GPIO_Init+0x226>
80016ee: 687b ldr r3, [r7, #4]
80016f0: 4a51 ldr r2, [pc, #324] ; (8001838 <HAL_GPIO_Init+0x318>)
80016f2: 4293 cmp r3, r2
80016f4: d025 beq.n 8001742 <HAL_GPIO_Init+0x222>
80016f6: 687b ldr r3, [r7, #4]
80016f8: 4a50 ldr r2, [pc, #320] ; (800183c <HAL_GPIO_Init+0x31c>)
80016fa: 4293 cmp r3, r2
80016fc: d01f beq.n 800173e <HAL_GPIO_Init+0x21e>
80016fe: 687b ldr r3, [r7, #4]
8001700: 4a4f ldr r2, [pc, #316] ; (8001840 <HAL_GPIO_Init+0x320>)
8001702: 4293 cmp r3, r2
8001704: d019 beq.n 800173a <HAL_GPIO_Init+0x21a>
8001706: 687b ldr r3, [r7, #4]
8001708: 4a4e ldr r2, [pc, #312] ; (8001844 <HAL_GPIO_Init+0x324>)
800170a: 4293 cmp r3, r2
800170c: d013 beq.n 8001736 <HAL_GPIO_Init+0x216>
800170e: 687b ldr r3, [r7, #4]
8001710: 4a4d ldr r2, [pc, #308] ; (8001848 <HAL_GPIO_Init+0x328>)
8001712: 4293 cmp r3, r2
8001714: d00d beq.n 8001732 <HAL_GPIO_Init+0x212>
8001716: 687b ldr r3, [r7, #4]
8001718: 4a4c ldr r2, [pc, #304] ; (800184c <HAL_GPIO_Init+0x32c>)
800171a: 4293 cmp r3, r2
800171c: d007 beq.n 800172e <HAL_GPIO_Init+0x20e>
800171e: 687b ldr r3, [r7, #4]
8001720: 4a4b ldr r2, [pc, #300] ; (8001850 <HAL_GPIO_Init+0x330>)
8001722: 4293 cmp r3, r2
8001724: d101 bne.n 800172a <HAL_GPIO_Init+0x20a>
8001726: 2307 movs r3, #7
8001728: e00e b.n 8001748 <HAL_GPIO_Init+0x228>
800172a: 2308 movs r3, #8
800172c: e00c b.n 8001748 <HAL_GPIO_Init+0x228>
800172e: 2306 movs r3, #6
8001730: e00a b.n 8001748 <HAL_GPIO_Init+0x228>
8001732: 2305 movs r3, #5
8001734: e008 b.n 8001748 <HAL_GPIO_Init+0x228>
8001736: 2304 movs r3, #4
8001738: e006 b.n 8001748 <HAL_GPIO_Init+0x228>
800173a: 2303 movs r3, #3
800173c: e004 b.n 8001748 <HAL_GPIO_Init+0x228>
800173e: 2302 movs r3, #2
8001740: e002 b.n 8001748 <HAL_GPIO_Init+0x228>
8001742: 2301 movs r3, #1
8001744: e000 b.n 8001748 <HAL_GPIO_Init+0x228>
8001746: 2300 movs r3, #0
8001748: 69fa ldr r2, [r7, #28]
800174a: f002 0203 and.w r2, r2, #3
800174e: 0092 lsls r2, r2, #2
8001750: 4093 lsls r3, r2
8001752: 69ba ldr r2, [r7, #24]
8001754: 4313 orrs r3, r2
8001756: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8001758: 4935 ldr r1, [pc, #212] ; (8001830 <HAL_GPIO_Init+0x310>)
800175a: 69fb ldr r3, [r7, #28]
800175c: 089b lsrs r3, r3, #2
800175e: 3302 adds r3, #2
8001760: 69ba ldr r2, [r7, #24]
8001762: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001766: 4b3b ldr r3, [pc, #236] ; (8001854 <HAL_GPIO_Init+0x334>)
8001768: 689b ldr r3, [r3, #8]
800176a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800176c: 693b ldr r3, [r7, #16]
800176e: 43db mvns r3, r3
8001770: 69ba ldr r2, [r7, #24]
8001772: 4013 ands r3, r2
8001774: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8001776: 683b ldr r3, [r7, #0]
8001778: 685b ldr r3, [r3, #4]
800177a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800177e: 2b00 cmp r3, #0
8001780: d003 beq.n 800178a <HAL_GPIO_Init+0x26a>
{
temp |= iocurrent;
8001782: 69ba ldr r2, [r7, #24]
8001784: 693b ldr r3, [r7, #16]
8001786: 4313 orrs r3, r2
8001788: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
800178a: 4a32 ldr r2, [pc, #200] ; (8001854 <HAL_GPIO_Init+0x334>)
800178c: 69bb ldr r3, [r7, #24]
800178e: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001790: 4b30 ldr r3, [pc, #192] ; (8001854 <HAL_GPIO_Init+0x334>)
8001792: 68db ldr r3, [r3, #12]
8001794: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001796: 693b ldr r3, [r7, #16]
8001798: 43db mvns r3, r3
800179a: 69ba ldr r2, [r7, #24]
800179c: 4013 ands r3, r2
800179e: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
80017a0: 683b ldr r3, [r7, #0]
80017a2: 685b ldr r3, [r3, #4]
80017a4: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80017a8: 2b00 cmp r3, #0
80017aa: d003 beq.n 80017b4 <HAL_GPIO_Init+0x294>
{
temp |= iocurrent;
80017ac: 69ba ldr r2, [r7, #24]
80017ae: 693b ldr r3, [r7, #16]
80017b0: 4313 orrs r3, r2
80017b2: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
80017b4: 4a27 ldr r2, [pc, #156] ; (8001854 <HAL_GPIO_Init+0x334>)
80017b6: 69bb ldr r3, [r7, #24]
80017b8: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
80017ba: 4b26 ldr r3, [pc, #152] ; (8001854 <HAL_GPIO_Init+0x334>)
80017bc: 685b ldr r3, [r3, #4]
80017be: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80017c0: 693b ldr r3, [r7, #16]
80017c2: 43db mvns r3, r3
80017c4: 69ba ldr r2, [r7, #24]
80017c6: 4013 ands r3, r2
80017c8: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
80017ca: 683b ldr r3, [r7, #0]
80017cc: 685b ldr r3, [r3, #4]
80017ce: f403 3300 and.w r3, r3, #131072 ; 0x20000
80017d2: 2b00 cmp r3, #0
80017d4: d003 beq.n 80017de <HAL_GPIO_Init+0x2be>
{
temp |= iocurrent;
80017d6: 69ba ldr r2, [r7, #24]
80017d8: 693b ldr r3, [r7, #16]
80017da: 4313 orrs r3, r2
80017dc: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
80017de: 4a1d ldr r2, [pc, #116] ; (8001854 <HAL_GPIO_Init+0x334>)
80017e0: 69bb ldr r3, [r7, #24]
80017e2: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80017e4: 4b1b ldr r3, [pc, #108] ; (8001854 <HAL_GPIO_Init+0x334>)
80017e6: 681b ldr r3, [r3, #0]
80017e8: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80017ea: 693b ldr r3, [r7, #16]
80017ec: 43db mvns r3, r3
80017ee: 69ba ldr r2, [r7, #24]
80017f0: 4013 ands r3, r2
80017f2: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80017f4: 683b ldr r3, [r7, #0]
80017f6: 685b ldr r3, [r3, #4]
80017f8: f403 3380 and.w r3, r3, #65536 ; 0x10000
80017fc: 2b00 cmp r3, #0
80017fe: d003 beq.n 8001808 <HAL_GPIO_Init+0x2e8>
{
temp |= iocurrent;
8001800: 69ba ldr r2, [r7, #24]
8001802: 693b ldr r3, [r7, #16]
8001804: 4313 orrs r3, r2
8001806: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8001808: 4a12 ldr r2, [pc, #72] ; (8001854 <HAL_GPIO_Init+0x334>)
800180a: 69bb ldr r3, [r7, #24]
800180c: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
800180e: 69fb ldr r3, [r7, #28]
8001810: 3301 adds r3, #1
8001812: 61fb str r3, [r7, #28]
8001814: 69fb ldr r3, [r7, #28]
8001816: 2b0f cmp r3, #15
8001818: f67f ae90 bls.w 800153c <HAL_GPIO_Init+0x1c>
}
}
}
}
800181c: bf00 nop
800181e: bf00 nop
8001820: 3724 adds r7, #36 ; 0x24
8001822: 46bd mov sp, r7
8001824: f85d 7b04 ldr.w r7, [sp], #4
8001828: 4770 bx lr
800182a: bf00 nop
800182c: 40023800 .word 0x40023800
8001830: 40013800 .word 0x40013800
8001834: 40020000 .word 0x40020000
8001838: 40020400 .word 0x40020400
800183c: 40020800 .word 0x40020800
8001840: 40020c00 .word 0x40020c00
8001844: 40021000 .word 0x40021000
8001848: 40021400 .word 0x40021400
800184c: 40021800 .word 0x40021800
8001850: 40021c00 .word 0x40021c00
8001854: 40013c00 .word 0x40013c00
08001858 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001858: b480 push {r7}
800185a: b083 sub sp, #12
800185c: af00 add r7, sp, #0
800185e: 6078 str r0, [r7, #4]
8001860: 460b mov r3, r1
8001862: 807b strh r3, [r7, #2]
8001864: 4613 mov r3, r2
8001866: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001868: 787b ldrb r3, [r7, #1]
800186a: 2b00 cmp r3, #0
800186c: d003 beq.n 8001876 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
800186e: 887a ldrh r2, [r7, #2]
8001870: 687b ldr r3, [r7, #4]
8001872: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8001874: e003 b.n 800187e <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
8001876: 887b ldrh r3, [r7, #2]
8001878: 041a lsls r2, r3, #16
800187a: 687b ldr r3, [r7, #4]
800187c: 619a str r2, [r3, #24]
}
800187e: bf00 nop
8001880: 370c adds r7, #12
8001882: 46bd mov sp, r7
8001884: f85d 7b04 ldr.w r7, [sp], #4
8001888: 4770 bx lr
0800188a <HAL_GPIO_TogglePin>:
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
* @param GPIO_Pin Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
800188a: b480 push {r7}
800188c: b085 sub sp, #20
800188e: af00 add r7, sp, #0
8001890: 6078 str r0, [r7, #4]
8001892: 460b mov r3, r1
8001894: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* get current Output Data Register value */
odr = GPIOx->ODR;
8001896: 687b ldr r3, [r7, #4]
8001898: 695b ldr r3, [r3, #20]
800189a: 60fb str r3, [r7, #12]
/* Set selected pins that were at low level, and reset ones that were high */
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
800189c: 887a ldrh r2, [r7, #2]
800189e: 68fb ldr r3, [r7, #12]
80018a0: 4013 ands r3, r2
80018a2: 041a lsls r2, r3, #16
80018a4: 68fb ldr r3, [r7, #12]
80018a6: 43d9 mvns r1, r3
80018a8: 887b ldrh r3, [r7, #2]
80018aa: 400b ands r3, r1
80018ac: 431a orrs r2, r3
80018ae: 687b ldr r3, [r7, #4]
80018b0: 619a str r2, [r3, #24]
}
80018b2: bf00 nop
80018b4: 3714 adds r7, #20
80018b6: 46bd mov sp, r7
80018b8: f85d 7b04 ldr.w r7, [sp], #4
80018bc: 4770 bx lr
...
080018c0 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80018c0: b580 push {r7, lr}
80018c2: b086 sub sp, #24
80018c4: af00 add r7, sp, #0
80018c6: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
80018c8: 687b ldr r3, [r7, #4]
80018ca: 2b00 cmp r3, #0
80018cc: d101 bne.n 80018d2 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80018ce: 2301 movs r3, #1
80018d0: e267 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80018d2: 687b ldr r3, [r7, #4]
80018d4: 681b ldr r3, [r3, #0]
80018d6: f003 0301 and.w r3, r3, #1
80018da: 2b00 cmp r3, #0
80018dc: d075 beq.n 80019ca <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80018de: 4b88 ldr r3, [pc, #544] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
80018e0: 689b ldr r3, [r3, #8]
80018e2: f003 030c and.w r3, r3, #12
80018e6: 2b04 cmp r3, #4
80018e8: d00c beq.n 8001904 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80018ea: 4b85 ldr r3, [pc, #532] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
80018ec: 689b ldr r3, [r3, #8]
80018ee: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80018f2: 2b08 cmp r3, #8
80018f4: d112 bne.n 800191c <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80018f6: 4b82 ldr r3, [pc, #520] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
80018f8: 685b ldr r3, [r3, #4]
80018fa: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80018fe: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8001902: d10b bne.n 800191c <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001904: 4b7e ldr r3, [pc, #504] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001906: 681b ldr r3, [r3, #0]
8001908: f403 3300 and.w r3, r3, #131072 ; 0x20000
800190c: 2b00 cmp r3, #0
800190e: d05b beq.n 80019c8 <HAL_RCC_OscConfig+0x108>
8001910: 687b ldr r3, [r7, #4]
8001912: 685b ldr r3, [r3, #4]
8001914: 2b00 cmp r3, #0
8001916: d157 bne.n 80019c8 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8001918: 2301 movs r3, #1
800191a: e242 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800191c: 687b ldr r3, [r7, #4]
800191e: 685b ldr r3, [r3, #4]
8001920: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8001924: d106 bne.n 8001934 <HAL_RCC_OscConfig+0x74>
8001926: 4b76 ldr r3, [pc, #472] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001928: 681b ldr r3, [r3, #0]
800192a: 4a75 ldr r2, [pc, #468] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
800192c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001930: 6013 str r3, [r2, #0]
8001932: e01d b.n 8001970 <HAL_RCC_OscConfig+0xb0>
8001934: 687b ldr r3, [r7, #4]
8001936: 685b ldr r3, [r3, #4]
8001938: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
800193c: d10c bne.n 8001958 <HAL_RCC_OscConfig+0x98>
800193e: 4b70 ldr r3, [pc, #448] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001940: 681b ldr r3, [r3, #0]
8001942: 4a6f ldr r2, [pc, #444] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001944: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001948: 6013 str r3, [r2, #0]
800194a: 4b6d ldr r3, [pc, #436] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
800194c: 681b ldr r3, [r3, #0]
800194e: 4a6c ldr r2, [pc, #432] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001950: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001954: 6013 str r3, [r2, #0]
8001956: e00b b.n 8001970 <HAL_RCC_OscConfig+0xb0>
8001958: 4b69 ldr r3, [pc, #420] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
800195a: 681b ldr r3, [r3, #0]
800195c: 4a68 ldr r2, [pc, #416] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
800195e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001962: 6013 str r3, [r2, #0]
8001964: 4b66 ldr r3, [pc, #408] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001966: 681b ldr r3, [r3, #0]
8001968: 4a65 ldr r2, [pc, #404] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
800196a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800196e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8001970: 687b ldr r3, [r7, #4]
8001972: 685b ldr r3, [r3, #4]
8001974: 2b00 cmp r3, #0
8001976: d013 beq.n 80019a0 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001978: f7ff f8aa bl 8000ad0 <HAL_GetTick>
800197c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800197e: e008 b.n 8001992 <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001980: f7ff f8a6 bl 8000ad0 <HAL_GetTick>
8001984: 4602 mov r2, r0
8001986: 693b ldr r3, [r7, #16]
8001988: 1ad3 subs r3, r2, r3
800198a: 2b64 cmp r3, #100 ; 0x64
800198c: d901 bls.n 8001992 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
800198e: 2303 movs r3, #3
8001990: e207 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001992: 4b5b ldr r3, [pc, #364] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001994: 681b ldr r3, [r3, #0]
8001996: f403 3300 and.w r3, r3, #131072 ; 0x20000
800199a: 2b00 cmp r3, #0
800199c: d0f0 beq.n 8001980 <HAL_RCC_OscConfig+0xc0>
800199e: e014 b.n 80019ca <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80019a0: f7ff f896 bl 8000ad0 <HAL_GetTick>
80019a4: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80019a6: e008 b.n 80019ba <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80019a8: f7ff f892 bl 8000ad0 <HAL_GetTick>
80019ac: 4602 mov r2, r0
80019ae: 693b ldr r3, [r7, #16]
80019b0: 1ad3 subs r3, r2, r3
80019b2: 2b64 cmp r3, #100 ; 0x64
80019b4: d901 bls.n 80019ba <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
80019b6: 2303 movs r3, #3
80019b8: e1f3 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80019ba: 4b51 ldr r3, [pc, #324] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
80019bc: 681b ldr r3, [r3, #0]
80019be: f403 3300 and.w r3, r3, #131072 ; 0x20000
80019c2: 2b00 cmp r3, #0
80019c4: d1f0 bne.n 80019a8 <HAL_RCC_OscConfig+0xe8>
80019c6: e000 b.n 80019ca <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80019c8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80019ca: 687b ldr r3, [r7, #4]
80019cc: 681b ldr r3, [r3, #0]
80019ce: f003 0302 and.w r3, r3, #2
80019d2: 2b00 cmp r3, #0
80019d4: d063 beq.n 8001a9e <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80019d6: 4b4a ldr r3, [pc, #296] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
80019d8: 689b ldr r3, [r3, #8]
80019da: f003 030c and.w r3, r3, #12
80019de: 2b00 cmp r3, #0
80019e0: d00b beq.n 80019fa <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80019e2: 4b47 ldr r3, [pc, #284] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
80019e4: 689b ldr r3, [r3, #8]
80019e6: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80019ea: 2b08 cmp r3, #8
80019ec: d11c bne.n 8001a28 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80019ee: 4b44 ldr r3, [pc, #272] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
80019f0: 685b ldr r3, [r3, #4]
80019f2: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80019f6: 2b00 cmp r3, #0
80019f8: d116 bne.n 8001a28 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80019fa: 4b41 ldr r3, [pc, #260] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
80019fc: 681b ldr r3, [r3, #0]
80019fe: f003 0302 and.w r3, r3, #2
8001a02: 2b00 cmp r3, #0
8001a04: d005 beq.n 8001a12 <HAL_RCC_OscConfig+0x152>
8001a06: 687b ldr r3, [r7, #4]
8001a08: 68db ldr r3, [r3, #12]
8001a0a: 2b01 cmp r3, #1
8001a0c: d001 beq.n 8001a12 <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
8001a0e: 2301 movs r3, #1
8001a10: e1c7 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001a12: 4b3b ldr r3, [pc, #236] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001a14: 681b ldr r3, [r3, #0]
8001a16: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001a1a: 687b ldr r3, [r7, #4]
8001a1c: 691b ldr r3, [r3, #16]
8001a1e: 00db lsls r3, r3, #3
8001a20: 4937 ldr r1, [pc, #220] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001a22: 4313 orrs r3, r2
8001a24: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001a26: e03a b.n 8001a9e <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8001a28: 687b ldr r3, [r7, #4]
8001a2a: 68db ldr r3, [r3, #12]
8001a2c: 2b00 cmp r3, #0
8001a2e: d020 beq.n 8001a72 <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001a30: 4b34 ldr r3, [pc, #208] ; (8001b04 <HAL_RCC_OscConfig+0x244>)
8001a32: 2201 movs r2, #1
8001a34: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001a36: f7ff f84b bl 8000ad0 <HAL_GetTick>
8001a3a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001a3c: e008 b.n 8001a50 <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001a3e: f7ff f847 bl 8000ad0 <HAL_GetTick>
8001a42: 4602 mov r2, r0
8001a44: 693b ldr r3, [r7, #16]
8001a46: 1ad3 subs r3, r2, r3
8001a48: 2b02 cmp r3, #2
8001a4a: d901 bls.n 8001a50 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8001a4c: 2303 movs r3, #3
8001a4e: e1a8 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001a50: 4b2b ldr r3, [pc, #172] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001a52: 681b ldr r3, [r3, #0]
8001a54: f003 0302 and.w r3, r3, #2
8001a58: 2b00 cmp r3, #0
8001a5a: d0f0 beq.n 8001a3e <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001a5c: 4b28 ldr r3, [pc, #160] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001a5e: 681b ldr r3, [r3, #0]
8001a60: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001a64: 687b ldr r3, [r7, #4]
8001a66: 691b ldr r3, [r3, #16]
8001a68: 00db lsls r3, r3, #3
8001a6a: 4925 ldr r1, [pc, #148] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001a6c: 4313 orrs r3, r2
8001a6e: 600b str r3, [r1, #0]
8001a70: e015 b.n 8001a9e <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001a72: 4b24 ldr r3, [pc, #144] ; (8001b04 <HAL_RCC_OscConfig+0x244>)
8001a74: 2200 movs r2, #0
8001a76: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001a78: f7ff f82a bl 8000ad0 <HAL_GetTick>
8001a7c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001a7e: e008 b.n 8001a92 <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001a80: f7ff f826 bl 8000ad0 <HAL_GetTick>
8001a84: 4602 mov r2, r0
8001a86: 693b ldr r3, [r7, #16]
8001a88: 1ad3 subs r3, r2, r3
8001a8a: 2b02 cmp r3, #2
8001a8c: d901 bls.n 8001a92 <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
8001a8e: 2303 movs r3, #3
8001a90: e187 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001a92: 4b1b ldr r3, [pc, #108] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001a94: 681b ldr r3, [r3, #0]
8001a96: f003 0302 and.w r3, r3, #2
8001a9a: 2b00 cmp r3, #0
8001a9c: d1f0 bne.n 8001a80 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001a9e: 687b ldr r3, [r7, #4]
8001aa0: 681b ldr r3, [r3, #0]
8001aa2: f003 0308 and.w r3, r3, #8
8001aa6: 2b00 cmp r3, #0
8001aa8: d036 beq.n 8001b18 <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
8001aaa: 687b ldr r3, [r7, #4]
8001aac: 695b ldr r3, [r3, #20]
8001aae: 2b00 cmp r3, #0
8001ab0: d016 beq.n 8001ae0 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001ab2: 4b15 ldr r3, [pc, #84] ; (8001b08 <HAL_RCC_OscConfig+0x248>)
8001ab4: 2201 movs r2, #1
8001ab6: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001ab8: f7ff f80a bl 8000ad0 <HAL_GetTick>
8001abc: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001abe: e008 b.n 8001ad2 <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001ac0: f7ff f806 bl 8000ad0 <HAL_GetTick>
8001ac4: 4602 mov r2, r0
8001ac6: 693b ldr r3, [r7, #16]
8001ac8: 1ad3 subs r3, r2, r3
8001aca: 2b02 cmp r3, #2
8001acc: d901 bls.n 8001ad2 <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
8001ace: 2303 movs r3, #3
8001ad0: e167 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001ad2: 4b0b ldr r3, [pc, #44] ; (8001b00 <HAL_RCC_OscConfig+0x240>)
8001ad4: 6f5b ldr r3, [r3, #116] ; 0x74
8001ad6: f003 0302 and.w r3, r3, #2
8001ada: 2b00 cmp r3, #0
8001adc: d0f0 beq.n 8001ac0 <HAL_RCC_OscConfig+0x200>
8001ade: e01b b.n 8001b18 <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001ae0: 4b09 ldr r3, [pc, #36] ; (8001b08 <HAL_RCC_OscConfig+0x248>)
8001ae2: 2200 movs r2, #0
8001ae4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001ae6: f7fe fff3 bl 8000ad0 <HAL_GetTick>
8001aea: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001aec: e00e b.n 8001b0c <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001aee: f7fe ffef bl 8000ad0 <HAL_GetTick>
8001af2: 4602 mov r2, r0
8001af4: 693b ldr r3, [r7, #16]
8001af6: 1ad3 subs r3, r2, r3
8001af8: 2b02 cmp r3, #2
8001afa: d907 bls.n 8001b0c <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
8001afc: 2303 movs r3, #3
8001afe: e150 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
8001b00: 40023800 .word 0x40023800
8001b04: 42470000 .word 0x42470000
8001b08: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001b0c: 4b88 ldr r3, [pc, #544] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001b0e: 6f5b ldr r3, [r3, #116] ; 0x74
8001b10: f003 0302 and.w r3, r3, #2
8001b14: 2b00 cmp r3, #0
8001b16: d1ea bne.n 8001aee <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001b18: 687b ldr r3, [r7, #4]
8001b1a: 681b ldr r3, [r3, #0]
8001b1c: f003 0304 and.w r3, r3, #4
8001b20: 2b00 cmp r3, #0
8001b22: f000 8097 beq.w 8001c54 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
8001b26: 2300 movs r3, #0
8001b28: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8001b2a: 4b81 ldr r3, [pc, #516] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001b2c: 6c1b ldr r3, [r3, #64] ; 0x40
8001b2e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001b32: 2b00 cmp r3, #0
8001b34: d10f bne.n 8001b56 <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001b36: 2300 movs r3, #0
8001b38: 60bb str r3, [r7, #8]
8001b3a: 4b7d ldr r3, [pc, #500] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001b3c: 6c1b ldr r3, [r3, #64] ; 0x40
8001b3e: 4a7c ldr r2, [pc, #496] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001b40: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001b44: 6413 str r3, [r2, #64] ; 0x40
8001b46: 4b7a ldr r3, [pc, #488] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001b48: 6c1b ldr r3, [r3, #64] ; 0x40
8001b4a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001b4e: 60bb str r3, [r7, #8]
8001b50: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001b52: 2301 movs r3, #1
8001b54: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001b56: 4b77 ldr r3, [pc, #476] ; (8001d34 <HAL_RCC_OscConfig+0x474>)
8001b58: 681b ldr r3, [r3, #0]
8001b5a: f403 7380 and.w r3, r3, #256 ; 0x100
8001b5e: 2b00 cmp r3, #0
8001b60: d118 bne.n 8001b94 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001b62: 4b74 ldr r3, [pc, #464] ; (8001d34 <HAL_RCC_OscConfig+0x474>)
8001b64: 681b ldr r3, [r3, #0]
8001b66: 4a73 ldr r2, [pc, #460] ; (8001d34 <HAL_RCC_OscConfig+0x474>)
8001b68: f443 7380 orr.w r3, r3, #256 ; 0x100
8001b6c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001b6e: f7fe ffaf bl 8000ad0 <HAL_GetTick>
8001b72: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001b74: e008 b.n 8001b88 <HAL_RCC_OscConfig+0x2c8>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001b76: f7fe ffab bl 8000ad0 <HAL_GetTick>
8001b7a: 4602 mov r2, r0
8001b7c: 693b ldr r3, [r7, #16]
8001b7e: 1ad3 subs r3, r2, r3
8001b80: 2b02 cmp r3, #2
8001b82: d901 bls.n 8001b88 <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
8001b84: 2303 movs r3, #3
8001b86: e10c b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001b88: 4b6a ldr r3, [pc, #424] ; (8001d34 <HAL_RCC_OscConfig+0x474>)
8001b8a: 681b ldr r3, [r3, #0]
8001b8c: f403 7380 and.w r3, r3, #256 ; 0x100
8001b90: 2b00 cmp r3, #0
8001b92: d0f0 beq.n 8001b76 <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001b94: 687b ldr r3, [r7, #4]
8001b96: 689b ldr r3, [r3, #8]
8001b98: 2b01 cmp r3, #1
8001b9a: d106 bne.n 8001baa <HAL_RCC_OscConfig+0x2ea>
8001b9c: 4b64 ldr r3, [pc, #400] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001b9e: 6f1b ldr r3, [r3, #112] ; 0x70
8001ba0: 4a63 ldr r2, [pc, #396] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001ba2: f043 0301 orr.w r3, r3, #1
8001ba6: 6713 str r3, [r2, #112] ; 0x70
8001ba8: e01c b.n 8001be4 <HAL_RCC_OscConfig+0x324>
8001baa: 687b ldr r3, [r7, #4]
8001bac: 689b ldr r3, [r3, #8]
8001bae: 2b05 cmp r3, #5
8001bb0: d10c bne.n 8001bcc <HAL_RCC_OscConfig+0x30c>
8001bb2: 4b5f ldr r3, [pc, #380] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001bb4: 6f1b ldr r3, [r3, #112] ; 0x70
8001bb6: 4a5e ldr r2, [pc, #376] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001bb8: f043 0304 orr.w r3, r3, #4
8001bbc: 6713 str r3, [r2, #112] ; 0x70
8001bbe: 4b5c ldr r3, [pc, #368] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001bc0: 6f1b ldr r3, [r3, #112] ; 0x70
8001bc2: 4a5b ldr r2, [pc, #364] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001bc4: f043 0301 orr.w r3, r3, #1
8001bc8: 6713 str r3, [r2, #112] ; 0x70
8001bca: e00b b.n 8001be4 <HAL_RCC_OscConfig+0x324>
8001bcc: 4b58 ldr r3, [pc, #352] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001bce: 6f1b ldr r3, [r3, #112] ; 0x70
8001bd0: 4a57 ldr r2, [pc, #348] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001bd2: f023 0301 bic.w r3, r3, #1
8001bd6: 6713 str r3, [r2, #112] ; 0x70
8001bd8: 4b55 ldr r3, [pc, #340] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001bda: 6f1b ldr r3, [r3, #112] ; 0x70
8001bdc: 4a54 ldr r2, [pc, #336] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001bde: f023 0304 bic.w r3, r3, #4
8001be2: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8001be4: 687b ldr r3, [r7, #4]
8001be6: 689b ldr r3, [r3, #8]
8001be8: 2b00 cmp r3, #0
8001bea: d015 beq.n 8001c18 <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001bec: f7fe ff70 bl 8000ad0 <HAL_GetTick>
8001bf0: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001bf2: e00a b.n 8001c0a <HAL_RCC_OscConfig+0x34a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001bf4: f7fe ff6c bl 8000ad0 <HAL_GetTick>
8001bf8: 4602 mov r2, r0
8001bfa: 693b ldr r3, [r7, #16]
8001bfc: 1ad3 subs r3, r2, r3
8001bfe: f241 3288 movw r2, #5000 ; 0x1388
8001c02: 4293 cmp r3, r2
8001c04: d901 bls.n 8001c0a <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
8001c06: 2303 movs r3, #3
8001c08: e0cb b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001c0a: 4b49 ldr r3, [pc, #292] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001c0c: 6f1b ldr r3, [r3, #112] ; 0x70
8001c0e: f003 0302 and.w r3, r3, #2
8001c12: 2b00 cmp r3, #0
8001c14: d0ee beq.n 8001bf4 <HAL_RCC_OscConfig+0x334>
8001c16: e014 b.n 8001c42 <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001c18: f7fe ff5a bl 8000ad0 <HAL_GetTick>
8001c1c: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001c1e: e00a b.n 8001c36 <HAL_RCC_OscConfig+0x376>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001c20: f7fe ff56 bl 8000ad0 <HAL_GetTick>
8001c24: 4602 mov r2, r0
8001c26: 693b ldr r3, [r7, #16]
8001c28: 1ad3 subs r3, r2, r3
8001c2a: f241 3288 movw r2, #5000 ; 0x1388
8001c2e: 4293 cmp r3, r2
8001c30: d901 bls.n 8001c36 <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
8001c32: 2303 movs r3, #3
8001c34: e0b5 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001c36: 4b3e ldr r3, [pc, #248] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001c38: 6f1b ldr r3, [r3, #112] ; 0x70
8001c3a: f003 0302 and.w r3, r3, #2
8001c3e: 2b00 cmp r3, #0
8001c40: d1ee bne.n 8001c20 <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8001c42: 7dfb ldrb r3, [r7, #23]
8001c44: 2b01 cmp r3, #1
8001c46: d105 bne.n 8001c54 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001c48: 4b39 ldr r3, [pc, #228] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001c4a: 6c1b ldr r3, [r3, #64] ; 0x40
8001c4c: 4a38 ldr r2, [pc, #224] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001c4e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8001c52: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001c54: 687b ldr r3, [r7, #4]
8001c56: 699b ldr r3, [r3, #24]
8001c58: 2b00 cmp r3, #0
8001c5a: f000 80a1 beq.w 8001da0 <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8001c5e: 4b34 ldr r3, [pc, #208] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001c60: 689b ldr r3, [r3, #8]
8001c62: f003 030c and.w r3, r3, #12
8001c66: 2b08 cmp r3, #8
8001c68: d05c beq.n 8001d24 <HAL_RCC_OscConfig+0x464>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001c6a: 687b ldr r3, [r7, #4]
8001c6c: 699b ldr r3, [r3, #24]
8001c6e: 2b02 cmp r3, #2
8001c70: d141 bne.n 8001cf6 <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001c72: 4b31 ldr r3, [pc, #196] ; (8001d38 <HAL_RCC_OscConfig+0x478>)
8001c74: 2200 movs r2, #0
8001c76: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001c78: f7fe ff2a bl 8000ad0 <HAL_GetTick>
8001c7c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001c7e: e008 b.n 8001c92 <HAL_RCC_OscConfig+0x3d2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001c80: f7fe ff26 bl 8000ad0 <HAL_GetTick>
8001c84: 4602 mov r2, r0
8001c86: 693b ldr r3, [r7, #16]
8001c88: 1ad3 subs r3, r2, r3
8001c8a: 2b02 cmp r3, #2
8001c8c: d901 bls.n 8001c92 <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
8001c8e: 2303 movs r3, #3
8001c90: e087 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001c92: 4b27 ldr r3, [pc, #156] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001c94: 681b ldr r3, [r3, #0]
8001c96: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001c9a: 2b00 cmp r3, #0
8001c9c: d1f0 bne.n 8001c80 <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
8001c9e: 687b ldr r3, [r7, #4]
8001ca0: 69da ldr r2, [r3, #28]
8001ca2: 687b ldr r3, [r7, #4]
8001ca4: 6a1b ldr r3, [r3, #32]
8001ca6: 431a orrs r2, r3
8001ca8: 687b ldr r3, [r7, #4]
8001caa: 6a5b ldr r3, [r3, #36] ; 0x24
8001cac: 019b lsls r3, r3, #6
8001cae: 431a orrs r2, r3
8001cb0: 687b ldr r3, [r7, #4]
8001cb2: 6a9b ldr r3, [r3, #40] ; 0x28
8001cb4: 085b lsrs r3, r3, #1
8001cb6: 3b01 subs r3, #1
8001cb8: 041b lsls r3, r3, #16
8001cba: 431a orrs r2, r3
8001cbc: 687b ldr r3, [r7, #4]
8001cbe: 6adb ldr r3, [r3, #44] ; 0x2c
8001cc0: 061b lsls r3, r3, #24
8001cc2: 491b ldr r1, [pc, #108] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001cc4: 4313 orrs r3, r2
8001cc6: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001cc8: 4b1b ldr r3, [pc, #108] ; (8001d38 <HAL_RCC_OscConfig+0x478>)
8001cca: 2201 movs r2, #1
8001ccc: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001cce: f7fe feff bl 8000ad0 <HAL_GetTick>
8001cd2: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001cd4: e008 b.n 8001ce8 <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001cd6: f7fe fefb bl 8000ad0 <HAL_GetTick>
8001cda: 4602 mov r2, r0
8001cdc: 693b ldr r3, [r7, #16]
8001cde: 1ad3 subs r3, r2, r3
8001ce0: 2b02 cmp r3, #2
8001ce2: d901 bls.n 8001ce8 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
8001ce4: 2303 movs r3, #3
8001ce6: e05c b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001ce8: 4b11 ldr r3, [pc, #68] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001cea: 681b ldr r3, [r3, #0]
8001cec: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001cf0: 2b00 cmp r3, #0
8001cf2: d0f0 beq.n 8001cd6 <HAL_RCC_OscConfig+0x416>
8001cf4: e054 b.n 8001da0 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001cf6: 4b10 ldr r3, [pc, #64] ; (8001d38 <HAL_RCC_OscConfig+0x478>)
8001cf8: 2200 movs r2, #0
8001cfa: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001cfc: f7fe fee8 bl 8000ad0 <HAL_GetTick>
8001d00: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001d02: e008 b.n 8001d16 <HAL_RCC_OscConfig+0x456>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001d04: f7fe fee4 bl 8000ad0 <HAL_GetTick>
8001d08: 4602 mov r2, r0
8001d0a: 693b ldr r3, [r7, #16]
8001d0c: 1ad3 subs r3, r2, r3
8001d0e: 2b02 cmp r3, #2
8001d10: d901 bls.n 8001d16 <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
8001d12: 2303 movs r3, #3
8001d14: e045 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001d16: 4b06 ldr r3, [pc, #24] ; (8001d30 <HAL_RCC_OscConfig+0x470>)
8001d18: 681b ldr r3, [r3, #0]
8001d1a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001d1e: 2b00 cmp r3, #0
8001d20: d1f0 bne.n 8001d04 <HAL_RCC_OscConfig+0x444>
8001d22: e03d b.n 8001da0 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001d24: 687b ldr r3, [r7, #4]
8001d26: 699b ldr r3, [r3, #24]
8001d28: 2b01 cmp r3, #1
8001d2a: d107 bne.n 8001d3c <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
8001d2c: 2301 movs r3, #1
8001d2e: e038 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
8001d30: 40023800 .word 0x40023800
8001d34: 40007000 .word 0x40007000
8001d38: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8001d3c: 4b1b ldr r3, [pc, #108] ; (8001dac <HAL_RCC_OscConfig+0x4ec>)
8001d3e: 685b ldr r3, [r3, #4]
8001d40: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001d42: 687b ldr r3, [r7, #4]
8001d44: 699b ldr r3, [r3, #24]
8001d46: 2b01 cmp r3, #1
8001d48: d028 beq.n 8001d9c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001d4a: 68fb ldr r3, [r7, #12]
8001d4c: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8001d50: 687b ldr r3, [r7, #4]
8001d52: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001d54: 429a cmp r2, r3
8001d56: d121 bne.n 8001d9c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001d58: 68fb ldr r3, [r7, #12]
8001d5a: f003 023f and.w r2, r3, #63 ; 0x3f
8001d5e: 687b ldr r3, [r7, #4]
8001d60: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001d62: 429a cmp r2, r3
8001d64: d11a bne.n 8001d9c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001d66: 68fa ldr r2, [r7, #12]
8001d68: f647 73c0 movw r3, #32704 ; 0x7fc0
8001d6c: 4013 ands r3, r2
8001d6e: 687a ldr r2, [r7, #4]
8001d70: 6a52 ldr r2, [r2, #36] ; 0x24
8001d72: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001d74: 4293 cmp r3, r2
8001d76: d111 bne.n 8001d9c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8001d78: 68fb ldr r3, [r7, #12]
8001d7a: f403 3240 and.w r2, r3, #196608 ; 0x30000
8001d7e: 687b ldr r3, [r7, #4]
8001d80: 6a9b ldr r3, [r3, #40] ; 0x28
8001d82: 085b lsrs r3, r3, #1
8001d84: 3b01 subs r3, #1
8001d86: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001d88: 429a cmp r2, r3
8001d8a: d107 bne.n 8001d9c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8001d8c: 68fb ldr r3, [r7, #12]
8001d8e: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8001d92: 687b ldr r3, [r7, #4]
8001d94: 6adb ldr r3, [r3, #44] ; 0x2c
8001d96: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8001d98: 429a cmp r2, r3
8001d9a: d001 beq.n 8001da0 <HAL_RCC_OscConfig+0x4e0>
#endif
{
return HAL_ERROR;
8001d9c: 2301 movs r3, #1
8001d9e: e000 b.n 8001da2 <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
8001da0: 2300 movs r3, #0
}
8001da2: 4618 mov r0, r3
8001da4: 3718 adds r7, #24
8001da6: 46bd mov sp, r7
8001da8: bd80 pop {r7, pc}
8001daa: bf00 nop
8001dac: 40023800 .word 0x40023800
08001db0 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001db0: b580 push {r7, lr}
8001db2: b084 sub sp, #16
8001db4: af00 add r7, sp, #0
8001db6: 6078 str r0, [r7, #4]
8001db8: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8001dba: 687b ldr r3, [r7, #4]
8001dbc: 2b00 cmp r3, #0
8001dbe: d101 bne.n 8001dc4 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001dc0: 2301 movs r3, #1
8001dc2: e0cc b.n 8001f5e <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001dc4: 4b68 ldr r3, [pc, #416] ; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
8001dc6: 681b ldr r3, [r3, #0]
8001dc8: f003 0307 and.w r3, r3, #7
8001dcc: 683a ldr r2, [r7, #0]
8001dce: 429a cmp r2, r3
8001dd0: d90c bls.n 8001dec <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001dd2: 4b65 ldr r3, [pc, #404] ; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
8001dd4: 683a ldr r2, [r7, #0]
8001dd6: b2d2 uxtb r2, r2
8001dd8: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001dda: 4b63 ldr r3, [pc, #396] ; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
8001ddc: 681b ldr r3, [r3, #0]
8001dde: f003 0307 and.w r3, r3, #7
8001de2: 683a ldr r2, [r7, #0]
8001de4: 429a cmp r2, r3
8001de6: d001 beq.n 8001dec <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
8001de8: 2301 movs r3, #1
8001dea: e0b8 b.n 8001f5e <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8001dec: 687b ldr r3, [r7, #4]
8001dee: 681b ldr r3, [r3, #0]
8001df0: f003 0302 and.w r3, r3, #2
8001df4: 2b00 cmp r3, #0
8001df6: d020 beq.n 8001e3a <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001df8: 687b ldr r3, [r7, #4]
8001dfa: 681b ldr r3, [r3, #0]
8001dfc: f003 0304 and.w r3, r3, #4
8001e00: 2b00 cmp r3, #0
8001e02: d005 beq.n 8001e10 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001e04: 4b59 ldr r3, [pc, #356] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e06: 689b ldr r3, [r3, #8]
8001e08: 4a58 ldr r2, [pc, #352] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e0a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
8001e0e: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001e10: 687b ldr r3, [r7, #4]
8001e12: 681b ldr r3, [r3, #0]
8001e14: f003 0308 and.w r3, r3, #8
8001e18: 2b00 cmp r3, #0
8001e1a: d005 beq.n 8001e28 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8001e1c: 4b53 ldr r3, [pc, #332] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e1e: 689b ldr r3, [r3, #8]
8001e20: 4a52 ldr r2, [pc, #328] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e22: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8001e26: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001e28: 4b50 ldr r3, [pc, #320] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e2a: 689b ldr r3, [r3, #8]
8001e2c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001e30: 687b ldr r3, [r7, #4]
8001e32: 689b ldr r3, [r3, #8]
8001e34: 494d ldr r1, [pc, #308] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e36: 4313 orrs r3, r2
8001e38: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001e3a: 687b ldr r3, [r7, #4]
8001e3c: 681b ldr r3, [r3, #0]
8001e3e: f003 0301 and.w r3, r3, #1
8001e42: 2b00 cmp r3, #0
8001e44: d044 beq.n 8001ed0 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001e46: 687b ldr r3, [r7, #4]
8001e48: 685b ldr r3, [r3, #4]
8001e4a: 2b01 cmp r3, #1
8001e4c: d107 bne.n 8001e5e <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001e4e: 4b47 ldr r3, [pc, #284] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e50: 681b ldr r3, [r3, #0]
8001e52: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001e56: 2b00 cmp r3, #0
8001e58: d119 bne.n 8001e8e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001e5a: 2301 movs r3, #1
8001e5c: e07f b.n 8001f5e <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001e5e: 687b ldr r3, [r7, #4]
8001e60: 685b ldr r3, [r3, #4]
8001e62: 2b02 cmp r3, #2
8001e64: d003 beq.n 8001e6e <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8001e66: 687b ldr r3, [r7, #4]
8001e68: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001e6a: 2b03 cmp r3, #3
8001e6c: d107 bne.n 8001e7e <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001e6e: 4b3f ldr r3, [pc, #252] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e70: 681b ldr r3, [r3, #0]
8001e72: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001e76: 2b00 cmp r3, #0
8001e78: d109 bne.n 8001e8e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001e7a: 2301 movs r3, #1
8001e7c: e06f b.n 8001f5e <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001e7e: 4b3b ldr r3, [pc, #236] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e80: 681b ldr r3, [r3, #0]
8001e82: f003 0302 and.w r3, r3, #2
8001e86: 2b00 cmp r3, #0
8001e88: d101 bne.n 8001e8e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001e8a: 2301 movs r3, #1
8001e8c: e067 b.n 8001f5e <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001e8e: 4b37 ldr r3, [pc, #220] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e90: 689b ldr r3, [r3, #8]
8001e92: f023 0203 bic.w r2, r3, #3
8001e96: 687b ldr r3, [r7, #4]
8001e98: 685b ldr r3, [r3, #4]
8001e9a: 4934 ldr r1, [pc, #208] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001e9c: 4313 orrs r3, r2
8001e9e: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001ea0: f7fe fe16 bl 8000ad0 <HAL_GetTick>
8001ea4: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001ea6: e00a b.n 8001ebe <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001ea8: f7fe fe12 bl 8000ad0 <HAL_GetTick>
8001eac: 4602 mov r2, r0
8001eae: 68fb ldr r3, [r7, #12]
8001eb0: 1ad3 subs r3, r2, r3
8001eb2: f241 3288 movw r2, #5000 ; 0x1388
8001eb6: 4293 cmp r3, r2
8001eb8: d901 bls.n 8001ebe <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8001eba: 2303 movs r3, #3
8001ebc: e04f b.n 8001f5e <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001ebe: 4b2b ldr r3, [pc, #172] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001ec0: 689b ldr r3, [r3, #8]
8001ec2: f003 020c and.w r2, r3, #12
8001ec6: 687b ldr r3, [r7, #4]
8001ec8: 685b ldr r3, [r3, #4]
8001eca: 009b lsls r3, r3, #2
8001ecc: 429a cmp r2, r3
8001ece: d1eb bne.n 8001ea8 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001ed0: 4b25 ldr r3, [pc, #148] ; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
8001ed2: 681b ldr r3, [r3, #0]
8001ed4: f003 0307 and.w r3, r3, #7
8001ed8: 683a ldr r2, [r7, #0]
8001eda: 429a cmp r2, r3
8001edc: d20c bcs.n 8001ef8 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001ede: 4b22 ldr r3, [pc, #136] ; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
8001ee0: 683a ldr r2, [r7, #0]
8001ee2: b2d2 uxtb r2, r2
8001ee4: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001ee6: 4b20 ldr r3, [pc, #128] ; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
8001ee8: 681b ldr r3, [r3, #0]
8001eea: f003 0307 and.w r3, r3, #7
8001eee: 683a ldr r2, [r7, #0]
8001ef0: 429a cmp r2, r3
8001ef2: d001 beq.n 8001ef8 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
8001ef4: 2301 movs r3, #1
8001ef6: e032 b.n 8001f5e <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001ef8: 687b ldr r3, [r7, #4]
8001efa: 681b ldr r3, [r3, #0]
8001efc: f003 0304 and.w r3, r3, #4
8001f00: 2b00 cmp r3, #0
8001f02: d008 beq.n 8001f16 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001f04: 4b19 ldr r3, [pc, #100] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001f06: 689b ldr r3, [r3, #8]
8001f08: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8001f0c: 687b ldr r3, [r7, #4]
8001f0e: 68db ldr r3, [r3, #12]
8001f10: 4916 ldr r1, [pc, #88] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001f12: 4313 orrs r3, r2
8001f14: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001f16: 687b ldr r3, [r7, #4]
8001f18: 681b ldr r3, [r3, #0]
8001f1a: f003 0308 and.w r3, r3, #8
8001f1e: 2b00 cmp r3, #0
8001f20: d009 beq.n 8001f36 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8001f22: 4b12 ldr r3, [pc, #72] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001f24: 689b ldr r3, [r3, #8]
8001f26: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8001f2a: 687b ldr r3, [r7, #4]
8001f2c: 691b ldr r3, [r3, #16]
8001f2e: 00db lsls r3, r3, #3
8001f30: 490e ldr r1, [pc, #56] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001f32: 4313 orrs r3, r2
8001f34: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8001f36: f000 f821 bl 8001f7c <HAL_RCC_GetSysClockFreq>
8001f3a: 4602 mov r2, r0
8001f3c: 4b0b ldr r3, [pc, #44] ; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
8001f3e: 689b ldr r3, [r3, #8]
8001f40: 091b lsrs r3, r3, #4
8001f42: f003 030f and.w r3, r3, #15
8001f46: 490a ldr r1, [pc, #40] ; (8001f70 <HAL_RCC_ClockConfig+0x1c0>)
8001f48: 5ccb ldrb r3, [r1, r3]
8001f4a: fa22 f303 lsr.w r3, r2, r3
8001f4e: 4a09 ldr r2, [pc, #36] ; (8001f74 <HAL_RCC_ClockConfig+0x1c4>)
8001f50: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
8001f52: 4b09 ldr r3, [pc, #36] ; (8001f78 <HAL_RCC_ClockConfig+0x1c8>)
8001f54: 681b ldr r3, [r3, #0]
8001f56: 4618 mov r0, r3
8001f58: f7fe fd76 bl 8000a48 <HAL_InitTick>
return HAL_OK;
8001f5c: 2300 movs r3, #0
}
8001f5e: 4618 mov r0, r3
8001f60: 3710 adds r7, #16
8001f62: 46bd mov sp, r7
8001f64: bd80 pop {r7, pc}
8001f66: bf00 nop
8001f68: 40023c00 .word 0x40023c00
8001f6c: 40023800 .word 0x40023800
8001f70: 08002c1c .word 0x08002c1c
8001f74: 20000000 .word 0x20000000
8001f78: 20000004 .word 0x20000004
08001f7c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001f7c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001f80: b090 sub sp, #64 ; 0x40
8001f82: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
8001f84: 2300 movs r3, #0
8001f86: 637b str r3, [r7, #52] ; 0x34
8001f88: 2300 movs r3, #0
8001f8a: 63fb str r3, [r7, #60] ; 0x3c
8001f8c: 2300 movs r3, #0
8001f8e: 633b str r3, [r7, #48] ; 0x30
uint32_t sysclockfreq = 0U;
8001f90: 2300 movs r3, #0
8001f92: 63bb str r3, [r7, #56] ; 0x38
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8001f94: 4b59 ldr r3, [pc, #356] ; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
8001f96: 689b ldr r3, [r3, #8]
8001f98: f003 030c and.w r3, r3, #12
8001f9c: 2b08 cmp r3, #8
8001f9e: d00d beq.n 8001fbc <HAL_RCC_GetSysClockFreq+0x40>
8001fa0: 2b08 cmp r3, #8
8001fa2: f200 80a1 bhi.w 80020e8 <HAL_RCC_GetSysClockFreq+0x16c>
8001fa6: 2b00 cmp r3, #0
8001fa8: d002 beq.n 8001fb0 <HAL_RCC_GetSysClockFreq+0x34>
8001faa: 2b04 cmp r3, #4
8001fac: d003 beq.n 8001fb6 <HAL_RCC_GetSysClockFreq+0x3a>
8001fae: e09b b.n 80020e8 <HAL_RCC_GetSysClockFreq+0x16c>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001fb0: 4b53 ldr r3, [pc, #332] ; (8002100 <HAL_RCC_GetSysClockFreq+0x184>)
8001fb2: 63bb str r3, [r7, #56] ; 0x38
break;
8001fb4: e09b b.n 80020ee <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8001fb6: 4b53 ldr r3, [pc, #332] ; (8002104 <HAL_RCC_GetSysClockFreq+0x188>)
8001fb8: 63bb str r3, [r7, #56] ; 0x38
break;
8001fba: e098 b.n 80020ee <HAL_RCC_GetSysClockFreq+0x172>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8001fbc: 4b4f ldr r3, [pc, #316] ; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
8001fbe: 685b ldr r3, [r3, #4]
8001fc0: f003 033f and.w r3, r3, #63 ; 0x3f
8001fc4: 637b str r3, [r7, #52] ; 0x34
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8001fc6: 4b4d ldr r3, [pc, #308] ; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
8001fc8: 685b ldr r3, [r3, #4]
8001fca: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8001fce: 2b00 cmp r3, #0
8001fd0: d028 beq.n 8002024 <HAL_RCC_GetSysClockFreq+0xa8>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001fd2: 4b4a ldr r3, [pc, #296] ; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
8001fd4: 685b ldr r3, [r3, #4]
8001fd6: 099b lsrs r3, r3, #6
8001fd8: 2200 movs r2, #0
8001fda: 623b str r3, [r7, #32]
8001fdc: 627a str r2, [r7, #36] ; 0x24
8001fde: 6a3b ldr r3, [r7, #32]
8001fe0: f3c3 0008 ubfx r0, r3, #0, #9
8001fe4: 2100 movs r1, #0
8001fe6: 4b47 ldr r3, [pc, #284] ; (8002104 <HAL_RCC_GetSysClockFreq+0x188>)
8001fe8: fb03 f201 mul.w r2, r3, r1
8001fec: 2300 movs r3, #0
8001fee: fb00 f303 mul.w r3, r0, r3
8001ff2: 4413 add r3, r2
8001ff4: 4a43 ldr r2, [pc, #268] ; (8002104 <HAL_RCC_GetSysClockFreq+0x188>)
8001ff6: fba0 1202 umull r1, r2, r0, r2
8001ffa: 62fa str r2, [r7, #44] ; 0x2c
8001ffc: 460a mov r2, r1
8001ffe: 62ba str r2, [r7, #40] ; 0x28
8002000: 6afa ldr r2, [r7, #44] ; 0x2c
8002002: 4413 add r3, r2
8002004: 62fb str r3, [r7, #44] ; 0x2c
8002006: 6b7b ldr r3, [r7, #52] ; 0x34
8002008: 2200 movs r2, #0
800200a: 61bb str r3, [r7, #24]
800200c: 61fa str r2, [r7, #28]
800200e: e9d7 2306 ldrd r2, r3, [r7, #24]
8002012: e9d7 010a ldrd r0, r1, [r7, #40] ; 0x28
8002016: f7fe f8d7 bl 80001c8 <__aeabi_uldivmod>
800201a: 4602 mov r2, r0
800201c: 460b mov r3, r1
800201e: 4613 mov r3, r2
8002020: 63fb str r3, [r7, #60] ; 0x3c
8002022: e053 b.n 80020cc <HAL_RCC_GetSysClockFreq+0x150>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8002024: 4b35 ldr r3, [pc, #212] ; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
8002026: 685b ldr r3, [r3, #4]
8002028: 099b lsrs r3, r3, #6
800202a: 2200 movs r2, #0
800202c: 613b str r3, [r7, #16]
800202e: 617a str r2, [r7, #20]
8002030: 693b ldr r3, [r7, #16]
8002032: f3c3 0a08 ubfx sl, r3, #0, #9
8002036: f04f 0b00 mov.w fp, #0
800203a: 4652 mov r2, sl
800203c: 465b mov r3, fp
800203e: f04f 0000 mov.w r0, #0
8002042: f04f 0100 mov.w r1, #0
8002046: 0159 lsls r1, r3, #5
8002048: ea41 61d2 orr.w r1, r1, r2, lsr #27
800204c: 0150 lsls r0, r2, #5
800204e: 4602 mov r2, r0
8002050: 460b mov r3, r1
8002052: ebb2 080a subs.w r8, r2, sl
8002056: eb63 090b sbc.w r9, r3, fp
800205a: f04f 0200 mov.w r2, #0
800205e: f04f 0300 mov.w r3, #0
8002062: ea4f 1389 mov.w r3, r9, lsl #6
8002066: ea43 6398 orr.w r3, r3, r8, lsr #26
800206a: ea4f 1288 mov.w r2, r8, lsl #6
800206e: ebb2 0408 subs.w r4, r2, r8
8002072: eb63 0509 sbc.w r5, r3, r9
8002076: f04f 0200 mov.w r2, #0
800207a: f04f 0300 mov.w r3, #0
800207e: 00eb lsls r3, r5, #3
8002080: ea43 7354 orr.w r3, r3, r4, lsr #29
8002084: 00e2 lsls r2, r4, #3
8002086: 4614 mov r4, r2
8002088: 461d mov r5, r3
800208a: eb14 030a adds.w r3, r4, sl
800208e: 603b str r3, [r7, #0]
8002090: eb45 030b adc.w r3, r5, fp
8002094: 607b str r3, [r7, #4]
8002096: f04f 0200 mov.w r2, #0
800209a: f04f 0300 mov.w r3, #0
800209e: e9d7 4500 ldrd r4, r5, [r7]
80020a2: 4629 mov r1, r5
80020a4: 028b lsls r3, r1, #10
80020a6: 4621 mov r1, r4
80020a8: ea43 5391 orr.w r3, r3, r1, lsr #22
80020ac: 4621 mov r1, r4
80020ae: 028a lsls r2, r1, #10
80020b0: 4610 mov r0, r2
80020b2: 4619 mov r1, r3
80020b4: 6b7b ldr r3, [r7, #52] ; 0x34
80020b6: 2200 movs r2, #0
80020b8: 60bb str r3, [r7, #8]
80020ba: 60fa str r2, [r7, #12]
80020bc: e9d7 2302 ldrd r2, r3, [r7, #8]
80020c0: f7fe f882 bl 80001c8 <__aeabi_uldivmod>
80020c4: 4602 mov r2, r0
80020c6: 460b mov r3, r1
80020c8: 4613 mov r3, r2
80020ca: 63fb str r3, [r7, #60] ; 0x3c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
80020cc: 4b0b ldr r3, [pc, #44] ; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
80020ce: 685b ldr r3, [r3, #4]
80020d0: 0c1b lsrs r3, r3, #16
80020d2: f003 0303 and.w r3, r3, #3
80020d6: 3301 adds r3, #1
80020d8: 005b lsls r3, r3, #1
80020da: 633b str r3, [r7, #48] ; 0x30
sysclockfreq = pllvco/pllp;
80020dc: 6bfa ldr r2, [r7, #60] ; 0x3c
80020de: 6b3b ldr r3, [r7, #48] ; 0x30
80020e0: fbb2 f3f3 udiv r3, r2, r3
80020e4: 63bb str r3, [r7, #56] ; 0x38
break;
80020e6: e002 b.n 80020ee <HAL_RCC_GetSysClockFreq+0x172>
}
default:
{
sysclockfreq = HSI_VALUE;
80020e8: 4b05 ldr r3, [pc, #20] ; (8002100 <HAL_RCC_GetSysClockFreq+0x184>)
80020ea: 63bb str r3, [r7, #56] ; 0x38
break;
80020ec: bf00 nop
}
}
return sysclockfreq;
80020ee: 6bbb ldr r3, [r7, #56] ; 0x38
}
80020f0: 4618 mov r0, r3
80020f2: 3740 adds r7, #64 ; 0x40
80020f4: 46bd mov sp, r7
80020f6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80020fa: bf00 nop
80020fc: 40023800 .word 0x40023800
8002100: 00f42400 .word 0x00f42400
8002104: 017d7840 .word 0x017d7840
08002108 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002108: b480 push {r7}
800210a: af00 add r7, sp, #0
return SystemCoreClock;
800210c: 4b03 ldr r3, [pc, #12] ; (800211c <HAL_RCC_GetHCLKFreq+0x14>)
800210e: 681b ldr r3, [r3, #0]
}
8002110: 4618 mov r0, r3
8002112: 46bd mov sp, r7
8002114: f85d 7b04 ldr.w r7, [sp], #4
8002118: 4770 bx lr
800211a: bf00 nop
800211c: 20000000 .word 0x20000000
08002120 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002120: b580 push {r7, lr}
8002122: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
8002124: f7ff fff0 bl 8002108 <HAL_RCC_GetHCLKFreq>
8002128: 4602 mov r2, r0
800212a: 4b05 ldr r3, [pc, #20] ; (8002140 <HAL_RCC_GetPCLK1Freq+0x20>)
800212c: 689b ldr r3, [r3, #8]
800212e: 0a9b lsrs r3, r3, #10
8002130: f003 0307 and.w r3, r3, #7
8002134: 4903 ldr r1, [pc, #12] ; (8002144 <HAL_RCC_GetPCLK1Freq+0x24>)
8002136: 5ccb ldrb r3, [r1, r3]
8002138: fa22 f303 lsr.w r3, r2, r3
}
800213c: 4618 mov r0, r3
800213e: bd80 pop {r7, pc}
8002140: 40023800 .word 0x40023800
8002144: 08002c2c .word 0x08002c2c
08002148 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8002148: b580 push {r7, lr}
800214a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
800214c: f7ff ffdc bl 8002108 <HAL_RCC_GetHCLKFreq>
8002150: 4602 mov r2, r0
8002152: 4b05 ldr r3, [pc, #20] ; (8002168 <HAL_RCC_GetPCLK2Freq+0x20>)
8002154: 689b ldr r3, [r3, #8]
8002156: 0b5b lsrs r3, r3, #13
8002158: f003 0307 and.w r3, r3, #7
800215c: 4903 ldr r1, [pc, #12] ; (800216c <HAL_RCC_GetPCLK2Freq+0x24>)
800215e: 5ccb ldrb r3, [r1, r3]
8002160: fa22 f303 lsr.w r3, r2, r3
}
8002164: 4618 mov r0, r3
8002166: bd80 pop {r7, pc}
8002168: 40023800 .word 0x40023800
800216c: 08002c2c .word 0x08002c2c
08002170 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8002170: b580 push {r7, lr}
8002172: b082 sub sp, #8
8002174: af00 add r7, sp, #0
8002176: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8002178: 687b ldr r3, [r7, #4]
800217a: 2b00 cmp r3, #0
800217c: d101 bne.n 8002182 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800217e: 2301 movs r3, #1
8002180: e03f b.n 8002202 <HAL_UART_Init+0x92>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8002182: 687b ldr r3, [r7, #4]
8002184: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002188: b2db uxtb r3, r3
800218a: 2b00 cmp r3, #0
800218c: d106 bne.n 800219c <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
800218e: 687b ldr r3, [r7, #4]
8002190: 2200 movs r2, #0
8002192: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8002196: 6878 ldr r0, [r7, #4]
8002198: f7fe fb86 bl 80008a8 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
800219c: 687b ldr r3, [r7, #4]
800219e: 2224 movs r2, #36 ; 0x24
80021a0: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
80021a4: 687b ldr r3, [r7, #4]
80021a6: 681b ldr r3, [r3, #0]
80021a8: 68da ldr r2, [r3, #12]
80021aa: 687b ldr r3, [r7, #4]
80021ac: 681b ldr r3, [r3, #0]
80021ae: f422 5200 bic.w r2, r2, #8192 ; 0x2000
80021b2: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
80021b4: 6878 ldr r0, [r7, #4]
80021b6: f000 f829 bl 800220c <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80021ba: 687b ldr r3, [r7, #4]
80021bc: 681b ldr r3, [r3, #0]
80021be: 691a ldr r2, [r3, #16]
80021c0: 687b ldr r3, [r7, #4]
80021c2: 681b ldr r3, [r3, #0]
80021c4: f422 4290 bic.w r2, r2, #18432 ; 0x4800
80021c8: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80021ca: 687b ldr r3, [r7, #4]
80021cc: 681b ldr r3, [r3, #0]
80021ce: 695a ldr r2, [r3, #20]
80021d0: 687b ldr r3, [r7, #4]
80021d2: 681b ldr r3, [r3, #0]
80021d4: f022 022a bic.w r2, r2, #42 ; 0x2a
80021d8: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
80021da: 687b ldr r3, [r7, #4]
80021dc: 681b ldr r3, [r3, #0]
80021de: 68da ldr r2, [r3, #12]
80021e0: 687b ldr r3, [r7, #4]
80021e2: 681b ldr r3, [r3, #0]
80021e4: f442 5200 orr.w r2, r2, #8192 ; 0x2000
80021e8: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80021ea: 687b ldr r3, [r7, #4]
80021ec: 2200 movs r2, #0
80021ee: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
80021f0: 687b ldr r3, [r7, #4]
80021f2: 2220 movs r2, #32
80021f4: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80021f8: 687b ldr r3, [r7, #4]
80021fa: 2220 movs r2, #32
80021fc: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8002200: 2300 movs r3, #0
}
8002202: 4618 mov r0, r3
8002204: 3708 adds r7, #8
8002206: 46bd mov sp, r7
8002208: bd80 pop {r7, pc}
...
0800220c <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
800220c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8002210: b0c0 sub sp, #256 ; 0x100
8002212: af00 add r7, sp, #0
8002214: f8c7 00f4 str.w r0, [r7, #244] ; 0xf4
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8002218: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800221c: 681b ldr r3, [r3, #0]
800221e: 691b ldr r3, [r3, #16]
8002220: f423 5040 bic.w r0, r3, #12288 ; 0x3000
8002224: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002228: 68d9 ldr r1, [r3, #12]
800222a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800222e: 681a ldr r2, [r3, #0]
8002230: ea40 0301 orr.w r3, r0, r1
8002234: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8002236: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800223a: 689a ldr r2, [r3, #8]
800223c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002240: 691b ldr r3, [r3, #16]
8002242: 431a orrs r2, r3
8002244: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002248: 695b ldr r3, [r3, #20]
800224a: 431a orrs r2, r3
800224c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002250: 69db ldr r3, [r3, #28]
8002252: 4313 orrs r3, r2
8002254: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8
MODIFY_REG(huart->Instance->CR1,
8002258: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800225c: 681b ldr r3, [r3, #0]
800225e: 68db ldr r3, [r3, #12]
8002260: f423 4116 bic.w r1, r3, #38400 ; 0x9600
8002264: f021 010c bic.w r1, r1, #12
8002268: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800226c: 681a ldr r2, [r3, #0]
800226e: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8
8002272: 430b orrs r3, r1
8002274: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8002276: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800227a: 681b ldr r3, [r3, #0]
800227c: 695b ldr r3, [r3, #20]
800227e: f423 7040 bic.w r0, r3, #768 ; 0x300
8002282: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002286: 6999 ldr r1, [r3, #24]
8002288: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800228c: 681a ldr r2, [r3, #0]
800228e: ea40 0301 orr.w r3, r0, r1
8002292: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
8002294: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002298: 681a ldr r2, [r3, #0]
800229a: 4b8f ldr r3, [pc, #572] ; (80024d8 <UART_SetConfig+0x2cc>)
800229c: 429a cmp r2, r3
800229e: d005 beq.n 80022ac <UART_SetConfig+0xa0>
80022a0: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80022a4: 681a ldr r2, [r3, #0]
80022a6: 4b8d ldr r3, [pc, #564] ; (80024dc <UART_SetConfig+0x2d0>)
80022a8: 429a cmp r2, r3
80022aa: d104 bne.n 80022b6 <UART_SetConfig+0xaa>
{
pclk = HAL_RCC_GetPCLK2Freq();
80022ac: f7ff ff4c bl 8002148 <HAL_RCC_GetPCLK2Freq>
80022b0: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
80022b4: e003 b.n 80022be <UART_SetConfig+0xb2>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
80022b6: f7ff ff33 bl 8002120 <HAL_RCC_GetPCLK1Freq>
80022ba: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80022be: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80022c2: 69db ldr r3, [r3, #28]
80022c4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80022c8: f040 810c bne.w 80024e4 <UART_SetConfig+0x2d8>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
80022cc: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
80022d0: 2200 movs r2, #0
80022d2: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
80022d6: f8c7 20ec str.w r2, [r7, #236] ; 0xec
80022da: e9d7 453a ldrd r4, r5, [r7, #232] ; 0xe8
80022de: 4622 mov r2, r4
80022e0: 462b mov r3, r5
80022e2: 1891 adds r1, r2, r2
80022e4: 65b9 str r1, [r7, #88] ; 0x58
80022e6: 415b adcs r3, r3
80022e8: 65fb str r3, [r7, #92] ; 0x5c
80022ea: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58
80022ee: 4621 mov r1, r4
80022f0: eb12 0801 adds.w r8, r2, r1
80022f4: 4629 mov r1, r5
80022f6: eb43 0901 adc.w r9, r3, r1
80022fa: f04f 0200 mov.w r2, #0
80022fe: f04f 0300 mov.w r3, #0
8002302: ea4f 03c9 mov.w r3, r9, lsl #3
8002306: ea43 7358 orr.w r3, r3, r8, lsr #29
800230a: ea4f 02c8 mov.w r2, r8, lsl #3
800230e: 4690 mov r8, r2
8002310: 4699 mov r9, r3
8002312: 4623 mov r3, r4
8002314: eb18 0303 adds.w r3, r8, r3
8002318: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
800231c: 462b mov r3, r5
800231e: eb49 0303 adc.w r3, r9, r3
8002322: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
8002326: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800232a: 685b ldr r3, [r3, #4]
800232c: 2200 movs r2, #0
800232e: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
8002332: f8c7 20dc str.w r2, [r7, #220] ; 0xdc
8002336: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8
800233a: 460b mov r3, r1
800233c: 18db adds r3, r3, r3
800233e: 653b str r3, [r7, #80] ; 0x50
8002340: 4613 mov r3, r2
8002342: eb42 0303 adc.w r3, r2, r3
8002346: 657b str r3, [r7, #84] ; 0x54
8002348: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50
800234c: e9d7 0138 ldrd r0, r1, [r7, #224] ; 0xe0
8002350: f7fd ff3a bl 80001c8 <__aeabi_uldivmod>
8002354: 4602 mov r2, r0
8002356: 460b mov r3, r1
8002358: 4b61 ldr r3, [pc, #388] ; (80024e0 <UART_SetConfig+0x2d4>)
800235a: fba3 2302 umull r2, r3, r3, r2
800235e: 095b lsrs r3, r3, #5
8002360: 011c lsls r4, r3, #4
8002362: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8002366: 2200 movs r2, #0
8002368: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
800236c: f8c7 20d4 str.w r2, [r7, #212] ; 0xd4
8002370: e9d7 8934 ldrd r8, r9, [r7, #208] ; 0xd0
8002374: 4642 mov r2, r8
8002376: 464b mov r3, r9
8002378: 1891 adds r1, r2, r2
800237a: 64b9 str r1, [r7, #72] ; 0x48
800237c: 415b adcs r3, r3
800237e: 64fb str r3, [r7, #76] ; 0x4c
8002380: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48
8002384: 4641 mov r1, r8
8002386: eb12 0a01 adds.w sl, r2, r1
800238a: 4649 mov r1, r9
800238c: eb43 0b01 adc.w fp, r3, r1
8002390: f04f 0200 mov.w r2, #0
8002394: f04f 0300 mov.w r3, #0
8002398: ea4f 03cb mov.w r3, fp, lsl #3
800239c: ea43 735a orr.w r3, r3, sl, lsr #29
80023a0: ea4f 02ca mov.w r2, sl, lsl #3
80023a4: 4692 mov sl, r2
80023a6: 469b mov fp, r3
80023a8: 4643 mov r3, r8
80023aa: eb1a 0303 adds.w r3, sl, r3
80023ae: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
80023b2: 464b mov r3, r9
80023b4: eb4b 0303 adc.w r3, fp, r3
80023b8: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
80023bc: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80023c0: 685b ldr r3, [r3, #4]
80023c2: 2200 movs r2, #0
80023c4: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
80023c8: f8c7 20c4 str.w r2, [r7, #196] ; 0xc4
80023cc: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0
80023d0: 460b mov r3, r1
80023d2: 18db adds r3, r3, r3
80023d4: 643b str r3, [r7, #64] ; 0x40
80023d6: 4613 mov r3, r2
80023d8: eb42 0303 adc.w r3, r2, r3
80023dc: 647b str r3, [r7, #68] ; 0x44
80023de: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
80023e2: e9d7 0132 ldrd r0, r1, [r7, #200] ; 0xc8
80023e6: f7fd feef bl 80001c8 <__aeabi_uldivmod>
80023ea: 4602 mov r2, r0
80023ec: 460b mov r3, r1
80023ee: 4611 mov r1, r2
80023f0: 4b3b ldr r3, [pc, #236] ; (80024e0 <UART_SetConfig+0x2d4>)
80023f2: fba3 2301 umull r2, r3, r3, r1
80023f6: 095b lsrs r3, r3, #5
80023f8: 2264 movs r2, #100 ; 0x64
80023fa: fb02 f303 mul.w r3, r2, r3
80023fe: 1acb subs r3, r1, r3
8002400: 00db lsls r3, r3, #3
8002402: f103 0232 add.w r2, r3, #50 ; 0x32
8002406: 4b36 ldr r3, [pc, #216] ; (80024e0 <UART_SetConfig+0x2d4>)
8002408: fba3 2302 umull r2, r3, r3, r2
800240c: 095b lsrs r3, r3, #5
800240e: 005b lsls r3, r3, #1
8002410: f403 73f8 and.w r3, r3, #496 ; 0x1f0
8002414: 441c add r4, r3
8002416: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800241a: 2200 movs r2, #0
800241c: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
8002420: f8c7 20bc str.w r2, [r7, #188] ; 0xbc
8002424: e9d7 892e ldrd r8, r9, [r7, #184] ; 0xb8
8002428: 4642 mov r2, r8
800242a: 464b mov r3, r9
800242c: 1891 adds r1, r2, r2
800242e: 63b9 str r1, [r7, #56] ; 0x38
8002430: 415b adcs r3, r3
8002432: 63fb str r3, [r7, #60] ; 0x3c
8002434: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38
8002438: 4641 mov r1, r8
800243a: 1851 adds r1, r2, r1
800243c: 6339 str r1, [r7, #48] ; 0x30
800243e: 4649 mov r1, r9
8002440: 414b adcs r3, r1
8002442: 637b str r3, [r7, #52] ; 0x34
8002444: f04f 0200 mov.w r2, #0
8002448: f04f 0300 mov.w r3, #0
800244c: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30
8002450: 4659 mov r1, fp
8002452: 00cb lsls r3, r1, #3
8002454: 4651 mov r1, sl
8002456: ea43 7351 orr.w r3, r3, r1, lsr #29
800245a: 4651 mov r1, sl
800245c: 00ca lsls r2, r1, #3
800245e: 4610 mov r0, r2
8002460: 4619 mov r1, r3
8002462: 4603 mov r3, r0
8002464: 4642 mov r2, r8
8002466: 189b adds r3, r3, r2
8002468: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
800246c: 464b mov r3, r9
800246e: 460a mov r2, r1
8002470: eb42 0303 adc.w r3, r2, r3
8002474: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
8002478: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800247c: 685b ldr r3, [r3, #4]
800247e: 2200 movs r2, #0
8002480: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
8002484: f8c7 20ac str.w r2, [r7, #172] ; 0xac
8002488: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8
800248c: 460b mov r3, r1
800248e: 18db adds r3, r3, r3
8002490: 62bb str r3, [r7, #40] ; 0x28
8002492: 4613 mov r3, r2
8002494: eb42 0303 adc.w r3, r2, r3
8002498: 62fb str r3, [r7, #44] ; 0x2c
800249a: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
800249e: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0
80024a2: f7fd fe91 bl 80001c8 <__aeabi_uldivmod>
80024a6: 4602 mov r2, r0
80024a8: 460b mov r3, r1
80024aa: 4b0d ldr r3, [pc, #52] ; (80024e0 <UART_SetConfig+0x2d4>)
80024ac: fba3 1302 umull r1, r3, r3, r2
80024b0: 095b lsrs r3, r3, #5
80024b2: 2164 movs r1, #100 ; 0x64
80024b4: fb01 f303 mul.w r3, r1, r3
80024b8: 1ad3 subs r3, r2, r3
80024ba: 00db lsls r3, r3, #3
80024bc: 3332 adds r3, #50 ; 0x32
80024be: 4a08 ldr r2, [pc, #32] ; (80024e0 <UART_SetConfig+0x2d4>)
80024c0: fba2 2303 umull r2, r3, r2, r3
80024c4: 095b lsrs r3, r3, #5
80024c6: f003 0207 and.w r2, r3, #7
80024ca: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024ce: 681b ldr r3, [r3, #0]
80024d0: 4422 add r2, r4
80024d2: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
80024d4: e106 b.n 80026e4 <UART_SetConfig+0x4d8>
80024d6: bf00 nop
80024d8: 40011000 .word 0x40011000
80024dc: 40011400 .word 0x40011400
80024e0: 51eb851f .word 0x51eb851f
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
80024e4: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
80024e8: 2200 movs r2, #0
80024ea: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
80024ee: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
80024f2: e9d7 8928 ldrd r8, r9, [r7, #160] ; 0xa0
80024f6: 4642 mov r2, r8
80024f8: 464b mov r3, r9
80024fa: 1891 adds r1, r2, r2
80024fc: 6239 str r1, [r7, #32]
80024fe: 415b adcs r3, r3
8002500: 627b str r3, [r7, #36] ; 0x24
8002502: e9d7 2308 ldrd r2, r3, [r7, #32]
8002506: 4641 mov r1, r8
8002508: 1854 adds r4, r2, r1
800250a: 4649 mov r1, r9
800250c: eb43 0501 adc.w r5, r3, r1
8002510: f04f 0200 mov.w r2, #0
8002514: f04f 0300 mov.w r3, #0
8002518: 00eb lsls r3, r5, #3
800251a: ea43 7354 orr.w r3, r3, r4, lsr #29
800251e: 00e2 lsls r2, r4, #3
8002520: 4614 mov r4, r2
8002522: 461d mov r5, r3
8002524: 4643 mov r3, r8
8002526: 18e3 adds r3, r4, r3
8002528: f8c7 3098 str.w r3, [r7, #152] ; 0x98
800252c: 464b mov r3, r9
800252e: eb45 0303 adc.w r3, r5, r3
8002532: f8c7 309c str.w r3, [r7, #156] ; 0x9c
8002536: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800253a: 685b ldr r3, [r3, #4]
800253c: 2200 movs r2, #0
800253e: f8c7 3090 str.w r3, [r7, #144] ; 0x90
8002542: f8c7 2094 str.w r2, [r7, #148] ; 0x94
8002546: f04f 0200 mov.w r2, #0
800254a: f04f 0300 mov.w r3, #0
800254e: e9d7 4524 ldrd r4, r5, [r7, #144] ; 0x90
8002552: 4629 mov r1, r5
8002554: 008b lsls r3, r1, #2
8002556: 4621 mov r1, r4
8002558: ea43 7391 orr.w r3, r3, r1, lsr #30
800255c: 4621 mov r1, r4
800255e: 008a lsls r2, r1, #2
8002560: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98
8002564: f7fd fe30 bl 80001c8 <__aeabi_uldivmod>
8002568: 4602 mov r2, r0
800256a: 460b mov r3, r1
800256c: 4b60 ldr r3, [pc, #384] ; (80026f0 <UART_SetConfig+0x4e4>)
800256e: fba3 2302 umull r2, r3, r3, r2
8002572: 095b lsrs r3, r3, #5
8002574: 011c lsls r4, r3, #4
8002576: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800257a: 2200 movs r2, #0
800257c: f8c7 3088 str.w r3, [r7, #136] ; 0x88
8002580: f8c7 208c str.w r2, [r7, #140] ; 0x8c
8002584: e9d7 8922 ldrd r8, r9, [r7, #136] ; 0x88
8002588: 4642 mov r2, r8
800258a: 464b mov r3, r9
800258c: 1891 adds r1, r2, r2
800258e: 61b9 str r1, [r7, #24]
8002590: 415b adcs r3, r3
8002592: 61fb str r3, [r7, #28]
8002594: e9d7 2306 ldrd r2, r3, [r7, #24]
8002598: 4641 mov r1, r8
800259a: 1851 adds r1, r2, r1
800259c: 6139 str r1, [r7, #16]
800259e: 4649 mov r1, r9
80025a0: 414b adcs r3, r1
80025a2: 617b str r3, [r7, #20]
80025a4: f04f 0200 mov.w r2, #0
80025a8: f04f 0300 mov.w r3, #0
80025ac: e9d7 ab04 ldrd sl, fp, [r7, #16]
80025b0: 4659 mov r1, fp
80025b2: 00cb lsls r3, r1, #3
80025b4: 4651 mov r1, sl
80025b6: ea43 7351 orr.w r3, r3, r1, lsr #29
80025ba: 4651 mov r1, sl
80025bc: 00ca lsls r2, r1, #3
80025be: 4610 mov r0, r2
80025c0: 4619 mov r1, r3
80025c2: 4603 mov r3, r0
80025c4: 4642 mov r2, r8
80025c6: 189b adds r3, r3, r2
80025c8: f8c7 3080 str.w r3, [r7, #128] ; 0x80
80025cc: 464b mov r3, r9
80025ce: 460a mov r2, r1
80025d0: eb42 0303 adc.w r3, r2, r3
80025d4: f8c7 3084 str.w r3, [r7, #132] ; 0x84
80025d8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80025dc: 685b ldr r3, [r3, #4]
80025de: 2200 movs r2, #0
80025e0: 67bb str r3, [r7, #120] ; 0x78
80025e2: 67fa str r2, [r7, #124] ; 0x7c
80025e4: f04f 0200 mov.w r2, #0
80025e8: f04f 0300 mov.w r3, #0
80025ec: e9d7 891e ldrd r8, r9, [r7, #120] ; 0x78
80025f0: 4649 mov r1, r9
80025f2: 008b lsls r3, r1, #2
80025f4: 4641 mov r1, r8
80025f6: ea43 7391 orr.w r3, r3, r1, lsr #30
80025fa: 4641 mov r1, r8
80025fc: 008a lsls r2, r1, #2
80025fe: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80
8002602: f7fd fde1 bl 80001c8 <__aeabi_uldivmod>
8002606: 4602 mov r2, r0
8002608: 460b mov r3, r1
800260a: 4611 mov r1, r2
800260c: 4b38 ldr r3, [pc, #224] ; (80026f0 <UART_SetConfig+0x4e4>)
800260e: fba3 2301 umull r2, r3, r3, r1
8002612: 095b lsrs r3, r3, #5
8002614: 2264 movs r2, #100 ; 0x64
8002616: fb02 f303 mul.w r3, r2, r3
800261a: 1acb subs r3, r1, r3
800261c: 011b lsls r3, r3, #4
800261e: 3332 adds r3, #50 ; 0x32
8002620: 4a33 ldr r2, [pc, #204] ; (80026f0 <UART_SetConfig+0x4e4>)
8002622: fba2 2303 umull r2, r3, r2, r3
8002626: 095b lsrs r3, r3, #5
8002628: f003 03f0 and.w r3, r3, #240 ; 0xf0
800262c: 441c add r4, r3
800262e: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8002632: 2200 movs r2, #0
8002634: 673b str r3, [r7, #112] ; 0x70
8002636: 677a str r2, [r7, #116] ; 0x74
8002638: e9d7 891c ldrd r8, r9, [r7, #112] ; 0x70
800263c: 4642 mov r2, r8
800263e: 464b mov r3, r9
8002640: 1891 adds r1, r2, r2
8002642: 60b9 str r1, [r7, #8]
8002644: 415b adcs r3, r3
8002646: 60fb str r3, [r7, #12]
8002648: e9d7 2302 ldrd r2, r3, [r7, #8]
800264c: 4641 mov r1, r8
800264e: 1851 adds r1, r2, r1
8002650: 6039 str r1, [r7, #0]
8002652: 4649 mov r1, r9
8002654: 414b adcs r3, r1
8002656: 607b str r3, [r7, #4]
8002658: f04f 0200 mov.w r2, #0
800265c: f04f 0300 mov.w r3, #0
8002660: e9d7 ab00 ldrd sl, fp, [r7]
8002664: 4659 mov r1, fp
8002666: 00cb lsls r3, r1, #3
8002668: 4651 mov r1, sl
800266a: ea43 7351 orr.w r3, r3, r1, lsr #29
800266e: 4651 mov r1, sl
8002670: 00ca lsls r2, r1, #3
8002672: 4610 mov r0, r2
8002674: 4619 mov r1, r3
8002676: 4603 mov r3, r0
8002678: 4642 mov r2, r8
800267a: 189b adds r3, r3, r2
800267c: 66bb str r3, [r7, #104] ; 0x68
800267e: 464b mov r3, r9
8002680: 460a mov r2, r1
8002682: eb42 0303 adc.w r3, r2, r3
8002686: 66fb str r3, [r7, #108] ; 0x6c
8002688: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800268c: 685b ldr r3, [r3, #4]
800268e: 2200 movs r2, #0
8002690: 663b str r3, [r7, #96] ; 0x60
8002692: 667a str r2, [r7, #100] ; 0x64
8002694: f04f 0200 mov.w r2, #0
8002698: f04f 0300 mov.w r3, #0
800269c: e9d7 8918 ldrd r8, r9, [r7, #96] ; 0x60
80026a0: 4649 mov r1, r9
80026a2: 008b lsls r3, r1, #2
80026a4: 4641 mov r1, r8
80026a6: ea43 7391 orr.w r3, r3, r1, lsr #30
80026aa: 4641 mov r1, r8
80026ac: 008a lsls r2, r1, #2
80026ae: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68
80026b2: f7fd fd89 bl 80001c8 <__aeabi_uldivmod>
80026b6: 4602 mov r2, r0
80026b8: 460b mov r3, r1
80026ba: 4b0d ldr r3, [pc, #52] ; (80026f0 <UART_SetConfig+0x4e4>)
80026bc: fba3 1302 umull r1, r3, r3, r2
80026c0: 095b lsrs r3, r3, #5
80026c2: 2164 movs r1, #100 ; 0x64
80026c4: fb01 f303 mul.w r3, r1, r3
80026c8: 1ad3 subs r3, r2, r3
80026ca: 011b lsls r3, r3, #4
80026cc: 3332 adds r3, #50 ; 0x32
80026ce: 4a08 ldr r2, [pc, #32] ; (80026f0 <UART_SetConfig+0x4e4>)
80026d0: fba2 2303 umull r2, r3, r2, r3
80026d4: 095b lsrs r3, r3, #5
80026d6: f003 020f and.w r2, r3, #15
80026da: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80026de: 681b ldr r3, [r3, #0]
80026e0: 4422 add r2, r4
80026e2: 609a str r2, [r3, #8]
}
80026e4: bf00 nop
80026e6: f507 7780 add.w r7, r7, #256 ; 0x100
80026ea: 46bd mov sp, r7
80026ec: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80026f0: 51eb851f .word 0x51eb851f
080026f4 <_ZN3sta17CanPendingRxFifosC1Emh>:
return ( (rxFlags_ >> idx_) & 0x1 );
}
CanPendingRxFifos::CanPendingRxFifos(uint32_t rxFlags, uint8_t numFifos)
80026f4: b480 push {r7}
80026f6: b085 sub sp, #20
80026f8: af00 add r7, sp, #0
80026fa: 60f8 str r0, [r7, #12]
80026fc: 60b9 str r1, [r7, #8]
80026fe: 4613 mov r3, r2
8002700: 71fb strb r3, [r7, #7]
: rxFlags_{rxFlags}, numFifos_{numFifos}
8002702: 68fb ldr r3, [r7, #12]
8002704: 68ba ldr r2, [r7, #8]
8002706: 601a str r2, [r3, #0]
8002708: 68fb ldr r3, [r7, #12]
800270a: 79fa ldrb r2, [r7, #7]
800270c: 711a strb r2, [r3, #4]
{}
800270e: 68fb ldr r3, [r7, #12]
8002710: 4618 mov r0, r3
8002712: 3714 adds r7, #20
8002714: 46bd mov sp, r7
8002716: f85d 7b04 ldr.w r7, [sp], #4
800271a: 4770 bx lr
0800271c <_ZN3sta13assert_failedEPKcS1_m>:
namespace sta
{
STA_WEAK
void assert_failed(const char * expr, const char * file, uint32_t line)
{
800271c: b480 push {r7}
800271e: b085 sub sp, #20
8002720: af00 add r7, sp, #0
8002722: 60f8 str r0, [r7, #12]
8002724: 60b9 str r1, [r7, #8]
8002726: 607a str r2, [r7, #4]
STA_DEBUG_PRINT(file);
STA_DEBUG_PRINT(':');
STA_DEBUG_PRINT(line);
STA_DEBUG_PRINT(": Assertion failed: ");
STA_DEBUG_PRINTLN(expr);
}
8002728: bf00 nop
800272a: 3714 adds r7, #20
800272c: 46bd mov sp, r7
800272e: f85d 7b04 ldr.w r7, [sp], #4
8002732: 4770 bx lr
08002734 <_ZN3sta11assert_haltEv>:
STA_WEAK
void assert_halt()
{
8002734: b480 push {r7}
8002736: af00 add r7, sp, #0
STA_BKPT();
8002738: be00 bkpt 0x0000
while (true);
800273a: e7fe b.n 800273a <_ZN3sta11assert_haltEv+0x6>
0800273c <_ZN3sta13CanControllerC1Ev>:
/**
* @brief CAN controller driver interface.
*
* @ingroup sta_core_can
*/
class CanController
800273c: b480 push {r7}
800273e: b083 sub sp, #12
8002740: af00 add r7, sp, #0
8002742: 6078 str r0, [r7, #4]
8002744: 4a04 ldr r2, [pc, #16] ; (8002758 <_ZN3sta13CanControllerC1Ev+0x1c>)
8002746: 687b ldr r3, [r7, #4]
8002748: 601a str r2, [r3, #0]
800274a: 687b ldr r3, [r7, #4]
800274c: 4618 mov r0, r3
800274e: 370c adds r7, #12
8002750: 46bd mov sp, r7
8002752: f85d 7b04 ldr.w r7, [sp], #4
8002756: 4770 bx lr
8002758: 08002c70 .word 0x08002c70
0800275c <_ZN3sta18STM32CanControllerC1EP19__CAN_HandleTypeDef>:
#include <sta/lang.hpp>
namespace sta
{
STM32CanController::STM32CanController(CAN_HandleTypeDef * handle)
800275c: b580 push {r7, lr}
800275e: b082 sub sp, #8
8002760: af00 add r7, sp, #0
8002762: 6078 str r0, [r7, #4]
8002764: 6039 str r1, [r7, #0]
: handle_{handle}
8002766: 687b ldr r3, [r7, #4]
8002768: 4618 mov r0, r3
800276a: f7ff ffe7 bl 800273c <_ZN3sta13CanControllerC1Ev>
800276e: 4a07 ldr r2, [pc, #28] ; (800278c <_ZN3sta18STM32CanControllerC1EP19__CAN_HandleTypeDef+0x30>)
8002770: 687b ldr r3, [r7, #4]
8002772: 601a str r2, [r3, #0]
8002774: 687b ldr r3, [r7, #4]
8002776: 683a ldr r2, [r7, #0]
8002778: 605a str r2, [r3, #4]
{
initFilters();
800277a: 6878 ldr r0, [r7, #4]
800277c: f000 f98f bl 8002a9e <_ZN3sta18STM32CanController11initFiltersEv>
}
8002780: 687b ldr r3, [r7, #4]
8002782: 4618 mov r0, r3
8002784: 3708 adds r7, #8
8002786: 46bd mov sp, r7
8002788: bd80 pop {r7, pc}
800278a: bf00 nop
800278c: 08002c3c .word 0x08002c3c
08002790 <_ZN3sta18STM32CanController5startEv>:
);
}
void STM32CanController::start()
{
8002790: b580 push {r7, lr}
8002792: b082 sub sp, #8
8002794: af00 add r7, sp, #0
8002796: 6078 str r0, [r7, #4]
HAL_CAN_Start(handle_);
8002798: 687b ldr r3, [r7, #4]
800279a: 685b ldr r3, [r3, #4]
800279c: 4618 mov r0, r3
800279e: f7fe fb7f bl 8000ea0 <HAL_CAN_Start>
}
80027a2: bf00 nop
80027a4: 3708 adds r7, #8
80027a6: 46bd mov sp, r7
80027a8: bd80 pop {r7, pc}
...
080027ac <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh>:
HAL_CAN_Stop(handle_);
}
bool STM32CanController::sendFrame(const CanTxHeader & header, const uint8_t * payload)
{
80027ac: b580 push {r7, lr}
80027ae: b08c sub sp, #48 ; 0x30
80027b0: af00 add r7, sp, #0
80027b2: 60f8 str r0, [r7, #12]
80027b4: 60b9 str r1, [r7, #8]
80027b6: 607a str r2, [r7, #4]
STA_ASSERT_MSG(header.payloadLength <= 8, "CAN 2.0B payload size exceeded");
80027b8: 68bb ldr r3, [r7, #8]
80027ba: 7b1b ldrb r3, [r3, #12]
80027bc: 2b08 cmp r3, #8
80027be: d906 bls.n 80027ce <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x22>
80027c0: 2226 movs r2, #38 ; 0x26
80027c2: 491a ldr r1, [pc, #104] ; (800282c <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x80>)
80027c4: 481a ldr r0, [pc, #104] ; (8002830 <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x84>)
80027c6: f7ff ffa9 bl 800271c <_ZN3sta13assert_failedEPKcS1_m>
80027ca: f7ff ffb3 bl 8002734 <_ZN3sta11assert_haltEv>
CAN_TxHeaderTypeDef halHeader;
if (header.id.format == CanIdFormat::STD)
80027ce: 68bb ldr r3, [r7, #8]
80027d0: 781b ldrb r3, [r3, #0]
80027d2: 2b00 cmp r3, #0
80027d4: d107 bne.n 80027e6 <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x3a>
{
halHeader.StdId = header.id.sid & 0x7FF;
80027d6: 68bb ldr r3, [r7, #8]
80027d8: 685b ldr r3, [r3, #4]
80027da: f3c3 030a ubfx r3, r3, #0, #11
80027de: 61bb str r3, [r7, #24]
halHeader.IDE = CAN_ID_STD;
80027e0: 2300 movs r3, #0
80027e2: 623b str r3, [r7, #32]
80027e4: e00c b.n 8002800 <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x54>
}
else
{
// Combine SID and EID
halHeader.ExtId = ((header.id.sid & 0x7FF) << 18) | (header.id.eid & 0x3FFFF);
80027e6: 68bb ldr r3, [r7, #8]
80027e8: 685b ldr r3, [r3, #4]
80027ea: 049a lsls r2, r3, #18
80027ec: 4b11 ldr r3, [pc, #68] ; (8002834 <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x88>)
80027ee: 4013 ands r3, r2
80027f0: 68ba ldr r2, [r7, #8]
80027f2: 6892 ldr r2, [r2, #8]
80027f4: f3c2 0211 ubfx r2, r2, #0, #18
80027f8: 4313 orrs r3, r2
80027fa: 61fb str r3, [r7, #28]
halHeader.IDE = CAN_ID_EXT;
80027fc: 2304 movs r3, #4
80027fe: 623b str r3, [r7, #32]
}
halHeader.DLC = header.payloadLength;
8002800: 68bb ldr r3, [r7, #8]
8002802: 7b1b ldrb r3, [r3, #12]
8002804: 62bb str r3, [r7, #40] ; 0x28
uint32_t mailbox; // Don't care
return (HAL_OK == HAL_CAN_AddTxMessage(handle_, &halHeader, const_cast<uint8_t *>(payload), &mailbox));
8002806: 68fb ldr r3, [r7, #12]
8002808: 6858 ldr r0, [r3, #4]
800280a: f107 0314 add.w r3, r7, #20
800280e: f107 0118 add.w r1, r7, #24
8002812: 687a ldr r2, [r7, #4]
8002814: f7fe fb88 bl 8000f28 <HAL_CAN_AddTxMessage>
8002818: 4603 mov r3, r0
800281a: 2b00 cmp r3, #0
800281c: bf0c ite eq
800281e: 2301 moveq r3, #1
8002820: 2300 movne r3, #0
8002822: b2db uxtb r3, r3
}
8002824: 4618 mov r0, r3
8002826: 3730 adds r7, #48 ; 0x30
8002828: 46bd mov sp, r7
800282a: bd80 pop {r7, pc}
800282c: 08002bd0 .word 0x08002bd0
8002830: 08002bfc .word 0x08002bfc
8002834: 1ffc0000 .word 0x1ffc0000
08002838 <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh>:
bool STM32CanController::receiveFrame(uint8_t fifo, CanRxHeader * header, uint8_t * payload)
{
8002838: b580 push {r7, lr}
800283a: b08c sub sp, #48 ; 0x30
800283c: af00 add r7, sp, #0
800283e: 60f8 str r0, [r7, #12]
8002840: 607a str r2, [r7, #4]
8002842: 603b str r3, [r7, #0]
8002844: 460b mov r3, r1
8002846: 72fb strb r3, [r7, #11]
// Check if message is available
if (HAL_CAN_GetRxFifoFillLevel(handle_, fifo) == 0)
8002848: 68fb ldr r3, [r7, #12]
800284a: 685b ldr r3, [r3, #4]
800284c: 7afa ldrb r2, [r7, #11]
800284e: 4611 mov r1, r2
8002850: 4618 mov r0, r3
8002852: f7fe fd56 bl 8001302 <HAL_CAN_GetRxFifoFillLevel>
8002856: 4603 mov r3, r0
8002858: 2b00 cmp r3, #0
800285a: bf0c ite eq
800285c: 2301 moveq r3, #1
800285e: 2300 movne r3, #0
8002860: b2db uxtb r3, r3
8002862: 2b00 cmp r3, #0
8002864: d001 beq.n 800286a <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh+0x32>
return false;
8002866: 2300 movs r3, #0
8002868: e02c b.n 80028c4 <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh+0x8c>
// Retrieve message
CAN_RxHeaderTypeDef halHeader;
HAL_CAN_GetRxMessage(handle_, fifo, &halHeader, payload);
800286a: 68fb ldr r3, [r7, #12]
800286c: 6858 ldr r0, [r3, #4]
800286e: 7af9 ldrb r1, [r7, #11]
8002870: f107 0214 add.w r2, r7, #20
8002874: 683b ldr r3, [r7, #0]
8002876: f7fe fc32 bl 80010de <HAL_CAN_GetRxMessage>
if (halHeader.IDE == CAN_ID_STD)
800287a: 69fb ldr r3, [r7, #28]
800287c: 2b00 cmp r3, #0
800287e: d109 bne.n 8002894 <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh+0x5c>
{
header->id.format = CanIdFormat::STD;
8002880: 687b ldr r3, [r7, #4]
8002882: 2200 movs r2, #0
8002884: 701a strb r2, [r3, #0]
header->id.sid = halHeader.StdId;
8002886: 697a ldr r2, [r7, #20]
8002888: 687b ldr r3, [r7, #4]
800288a: 605a str r2, [r3, #4]
header->id.eid = 0;
800288c: 687b ldr r3, [r7, #4]
800288e: 2200 movs r2, #0
8002890: 609a str r2, [r3, #8]
8002892: e00b b.n 80028ac <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh+0x74>
}
else
{
header->id.format = CanIdFormat::EXT;
8002894: 687b ldr r3, [r7, #4]
8002896: 2201 movs r2, #1
8002898: 701a strb r2, [r3, #0]
// Separate SID and EID
header->id.sid = (halHeader.ExtId >> 18);
800289a: 69bb ldr r3, [r7, #24]
800289c: 0c9a lsrs r2, r3, #18
800289e: 687b ldr r3, [r7, #4]
80028a0: 605a str r2, [r3, #4]
header->id.eid = halHeader.ExtId & 0x3FFFF;
80028a2: 69bb ldr r3, [r7, #24]
80028a4: f3c3 0211 ubfx r2, r3, #0, #18
80028a8: 687b ldr r3, [r7, #4]
80028aa: 609a str r2, [r3, #8]
}
// No conversion required for CAN 2B standard
header->payloadLength = halHeader.DLC;
80028ac: 6a7b ldr r3, [r7, #36] ; 0x24
80028ae: b2da uxtb r2, r3
80028b0: 687b ldr r3, [r7, #4]
80028b2: 731a strb r2, [r3, #12]
header->timestamp = halHeader.Timestamp;
80028b4: 6aba ldr r2, [r7, #40] ; 0x28
80028b6: 687b ldr r3, [r7, #4]
80028b8: 611a str r2, [r3, #16]
header->filter = halHeader.FilterMatchIndex;
80028ba: 6afb ldr r3, [r7, #44] ; 0x2c
80028bc: b2da uxtb r2, r3
80028be: 687b ldr r3, [r7, #4]
80028c0: 751a strb r2, [r3, #20]
return true;
80028c2: 2301 movs r3, #1
}
80028c4: 4618 mov r0, r3
80028c6: 3730 adds r7, #48 ; 0x30
80028c8: 46bd mov sp, r7
80028ca: bd80 pop {r7, pc}
080028cc <_ZN3sta18STM32CanController14getRxFifoFlagsEv>:
uint32_t STM32CanController::getRxFifoFlags()
{
80028cc: b590 push {r4, r7, lr}
80028ce: b083 sub sp, #12
80028d0: af00 add r7, sp, #0
80028d2: 6078 str r0, [r7, #4]
//
return (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO0) != 0)
80028d4: 687b ldr r3, [r7, #4]
80028d6: 685b ldr r3, [r3, #4]
80028d8: 2100 movs r1, #0
80028da: 4618 mov r0, r3
80028dc: f7fe fd11 bl 8001302 <HAL_CAN_GetRxFifoFillLevel>
80028e0: 4603 mov r3, r0
80028e2: 2b00 cmp r3, #0
80028e4: bf14 ite ne
80028e6: 2301 movne r3, #1
80028e8: 2300 moveq r3, #0
80028ea: b2db uxtb r3, r3
80028ec: 461c mov r4, r3
| (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO1) != 0) << 1;
80028ee: 687b ldr r3, [r7, #4]
80028f0: 685b ldr r3, [r3, #4]
80028f2: 2101 movs r1, #1
80028f4: 4618 mov r0, r3
80028f6: f7fe fd04 bl 8001302 <HAL_CAN_GetRxFifoFillLevel>
80028fa: 4603 mov r3, r0
80028fc: 2b00 cmp r3, #0
80028fe: d001 beq.n 8002904 <_ZN3sta18STM32CanController14getRxFifoFlagsEv+0x38>
8002900: 2302 movs r3, #2
8002902: e000 b.n 8002906 <_ZN3sta18STM32CanController14getRxFifoFlagsEv+0x3a>
8002904: 2300 movs r3, #0
8002906: 4323 orrs r3, r4
}
8002908: 4618 mov r0, r3
800290a: 370c adds r7, #12
800290c: 46bd mov sp, r7
800290e: bd90 pop {r4, r7, pc}
08002910 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb>:
void STM32CanController::configureFilter(uint8_t idx, const CanFilter & filter, bool active /* = false */)
{
8002910: b580 push {r7, lr}
8002912: b086 sub sp, #24
8002914: af00 add r7, sp, #0
8002916: 60f8 str r0, [r7, #12]
8002918: 607a str r2, [r7, #4]
800291a: 461a mov r2, r3
800291c: 460b mov r3, r1
800291e: 72fb strb r3, [r7, #11]
8002920: 4613 mov r3, r2
8002922: 72bb strb r3, [r7, #10]
CAN_FilterTypeDef * config = &filters_[idx];
8002924: 7afa ldrb r2, [r7, #11]
8002926: 4613 mov r3, r2
8002928: 009b lsls r3, r3, #2
800292a: 4413 add r3, r2
800292c: 00db lsls r3, r3, #3
800292e: 3308 adds r3, #8
8002930: 68fa ldr r2, [r7, #12]
8002932: 4413 add r3, r2
8002934: 617b str r3, [r7, #20]
if (filter.type == CanFilterIdFormat::STD)
8002936: 687b ldr r3, [r7, #4]
8002938: 691b ldr r3, [r3, #16]
800293a: 2b01 cmp r3, #1
800293c: d112 bne.n 8002964 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb+0x54>
{
config->FilterIdHigh = 0;
800293e: 697b ldr r3, [r7, #20]
8002940: 2200 movs r2, #0
8002942: 601a str r2, [r3, #0]
config->FilterIdLow = filter.obj.sid & 0x7FF;
8002944: 687b ldr r3, [r7, #4]
8002946: 681b ldr r3, [r3, #0]
8002948: f3c3 020a ubfx r2, r3, #0, #11
800294c: 697b ldr r3, [r7, #20]
800294e: 605a str r2, [r3, #4]
config->FilterMaskIdHigh = 0;
8002950: 697b ldr r3, [r7, #20]
8002952: 2200 movs r2, #0
8002954: 609a str r2, [r3, #8]
config->FilterMaskIdLow = filter.mask.sid & 0x7FF;
8002956: 687b ldr r3, [r7, #4]
8002958: 689b ldr r3, [r3, #8]
800295a: f3c3 020a ubfx r2, r3, #0, #11
800295e: 697b ldr r3, [r7, #20]
8002960: 60da str r2, [r3, #12]
8002962: e025 b.n 80029b0 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb+0xa0>
}
else
{
config->FilterIdHigh = ((filter.obj.sid & 0x7FF) << 2) | ((filter.obj.eid >> 16) & 0x3);
8002964: 687b ldr r3, [r7, #4]
8002966: 681b ldr r3, [r3, #0]
8002968: 009a lsls r2, r3, #2
800296a: f641 73fc movw r3, #8188 ; 0x1ffc
800296e: 4013 ands r3, r2
8002970: 687a ldr r2, [r7, #4]
8002972: 6852 ldr r2, [r2, #4]
8002974: 0c12 lsrs r2, r2, #16
8002976: f002 0203 and.w r2, r2, #3
800297a: 431a orrs r2, r3
800297c: 697b ldr r3, [r7, #20]
800297e: 601a str r2, [r3, #0]
config->FilterIdLow = filter.obj.eid & 0xFFFF;
8002980: 687b ldr r3, [r7, #4]
8002982: 685b ldr r3, [r3, #4]
8002984: b29a uxth r2, r3
8002986: 697b ldr r3, [r7, #20]
8002988: 605a str r2, [r3, #4]
config->FilterMaskIdHigh = ((filter.mask.sid & 0x7FF) << 2) | ((filter.mask.eid >> 16) & 0x3);
800298a: 687b ldr r3, [r7, #4]
800298c: 689b ldr r3, [r3, #8]
800298e: 009a lsls r2, r3, #2
8002990: f641 73fc movw r3, #8188 ; 0x1ffc
8002994: 4013 ands r3, r2
8002996: 687a ldr r2, [r7, #4]
8002998: 68d2 ldr r2, [r2, #12]
800299a: 0c12 lsrs r2, r2, #16
800299c: f002 0203 and.w r2, r2, #3
80029a0: 431a orrs r2, r3
80029a2: 697b ldr r3, [r7, #20]
80029a4: 609a str r2, [r3, #8]
config->FilterMaskIdLow = filter.mask.eid & 0xFFFF;
80029a6: 687b ldr r3, [r7, #4]
80029a8: 68db ldr r3, [r3, #12]
80029aa: b29a uxth r2, r3
80029ac: 697b ldr r3, [r7, #20]
80029ae: 60da str r2, [r3, #12]
}
config->FilterFIFOAssignment = filter.fifo;
80029b0: 687b ldr r3, [r7, #4]
80029b2: 7d1b ldrb r3, [r3, #20]
80029b4: 461a mov r2, r3
80029b6: 697b ldr r3, [r7, #20]
80029b8: 611a str r2, [r3, #16]
config->FilterActivation = (active ? CAN_FILTER_ENABLE : CAN_FILTER_DISABLE);
80029ba: 7abb ldrb r3, [r7, #10]
80029bc: 2b00 cmp r3, #0
80029be: d001 beq.n 80029c4 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb+0xb4>
80029c0: 2201 movs r2, #1
80029c2: e000 b.n 80029c6 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb+0xb6>
80029c4: 2200 movs r2, #0
80029c6: 697b ldr r3, [r7, #20]
80029c8: 621a str r2, [r3, #32]
HAL_CAN_ConfigFilter(handle_, config);
80029ca: 68fb ldr r3, [r7, #12]
80029cc: 685b ldr r3, [r3, #4]
80029ce: 6979 ldr r1, [r7, #20]
80029d0: 4618 mov r0, r3
80029d2: f7fe f985 bl 8000ce0 <HAL_CAN_ConfigFilter>
}
80029d6: bf00 nop
80029d8: 3718 adds r7, #24
80029da: 46bd mov sp, r7
80029dc: bd80 pop {r7, pc}
080029de <_ZN3sta18STM32CanController12enableFilterEh>:
void STM32CanController::enableFilter(uint8_t idx)
{
80029de: b580 push {r7, lr}
80029e0: b084 sub sp, #16
80029e2: af00 add r7, sp, #0
80029e4: 6078 str r0, [r7, #4]
80029e6: 460b mov r3, r1
80029e8: 70fb strb r3, [r7, #3]
CAN_FilterTypeDef * config = &filters_[idx];
80029ea: 78fa ldrb r2, [r7, #3]
80029ec: 4613 mov r3, r2
80029ee: 009b lsls r3, r3, #2
80029f0: 4413 add r3, r2
80029f2: 00db lsls r3, r3, #3
80029f4: 3308 adds r3, #8
80029f6: 687a ldr r2, [r7, #4]
80029f8: 4413 add r3, r2
80029fa: 60fb str r3, [r7, #12]
config->FilterActivation = CAN_FILTER_ENABLE;
80029fc: 68fb ldr r3, [r7, #12]
80029fe: 2201 movs r2, #1
8002a00: 621a str r2, [r3, #32]
HAL_CAN_ConfigFilter(handle_, config);
8002a02: 687b ldr r3, [r7, #4]
8002a04: 685b ldr r3, [r3, #4]
8002a06: 68f9 ldr r1, [r7, #12]
8002a08: 4618 mov r0, r3
8002a0a: f7fe f969 bl 8000ce0 <HAL_CAN_ConfigFilter>
}
8002a0e: bf00 nop
8002a10: 3710 adds r7, #16
8002a12: 46bd mov sp, r7
8002a14: bd80 pop {r7, pc}
08002a16 <_ZN3sta18STM32CanController13disableFilterEh>:
void STM32CanController::disableFilter(uint8_t idx)
{
8002a16: b580 push {r7, lr}
8002a18: b084 sub sp, #16
8002a1a: af00 add r7, sp, #0
8002a1c: 6078 str r0, [r7, #4]
8002a1e: 460b mov r3, r1
8002a20: 70fb strb r3, [r7, #3]
CAN_FilterTypeDef * config = &filters_[idx];
8002a22: 78fa ldrb r2, [r7, #3]
8002a24: 4613 mov r3, r2
8002a26: 009b lsls r3, r3, #2
8002a28: 4413 add r3, r2
8002a2a: 00db lsls r3, r3, #3
8002a2c: 3308 adds r3, #8
8002a2e: 687a ldr r2, [r7, #4]
8002a30: 4413 add r3, r2
8002a32: 60fb str r3, [r7, #12]
config->FilterActivation = CAN_FILTER_DISABLE;
8002a34: 68fb ldr r3, [r7, #12]
8002a36: 2200 movs r2, #0
8002a38: 621a str r2, [r3, #32]
HAL_CAN_ConfigFilter(handle_, config);
8002a3a: 687b ldr r3, [r7, #4]
8002a3c: 685b ldr r3, [r3, #4]
8002a3e: 68f9 ldr r1, [r7, #12]
8002a40: 4618 mov r0, r3
8002a42: f7fe f94d bl 8000ce0 <HAL_CAN_ConfigFilter>
}
8002a46: bf00 nop
8002a48: 3710 adds r7, #16
8002a4a: 46bd mov sp, r7
8002a4c: bd80 pop {r7, pc}
08002a4e <_ZN3sta18STM32CanController12clearFiltersEv>:
void STM32CanController::clearFilters()
{
8002a4e: b580 push {r7, lr}
8002a50: b084 sub sp, #16
8002a52: af00 add r7, sp, #0
8002a54: 6078 str r0, [r7, #4]
for (uint32_t i = 0; i < MAX_FILTER_COUNT; ++i)
8002a56: 2300 movs r3, #0
8002a58: 60fb str r3, [r7, #12]
8002a5a: e018 b.n 8002a8e <_ZN3sta18STM32CanController12clearFiltersEv+0x40>
{
CAN_FilterTypeDef * config = &filters_[i];
8002a5c: 68fa ldr r2, [r7, #12]
8002a5e: 4613 mov r3, r2
8002a60: 009b lsls r3, r3, #2
8002a62: 4413 add r3, r2
8002a64: 00db lsls r3, r3, #3
8002a66: 3308 adds r3, #8
8002a68: 687a ldr r2, [r7, #4]
8002a6a: 4413 add r3, r2
8002a6c: 60bb str r3, [r7, #8]
// Only disable active filters
if (config->FilterActivation == CAN_FILTER_ENABLE)
8002a6e: 68bb ldr r3, [r7, #8]
8002a70: 6a1b ldr r3, [r3, #32]
8002a72: 2b01 cmp r3, #1
8002a74: d108 bne.n 8002a88 <_ZN3sta18STM32CanController12clearFiltersEv+0x3a>
{
config->FilterActivation = CAN_FILTER_DISABLE;
8002a76: 68bb ldr r3, [r7, #8]
8002a78: 2200 movs r2, #0
8002a7a: 621a str r2, [r3, #32]
HAL_CAN_ConfigFilter(handle_, config);
8002a7c: 687b ldr r3, [r7, #4]
8002a7e: 685b ldr r3, [r3, #4]
8002a80: 68b9 ldr r1, [r7, #8]
8002a82: 4618 mov r0, r3
8002a84: f7fe f92c bl 8000ce0 <HAL_CAN_ConfigFilter>
for (uint32_t i = 0; i < MAX_FILTER_COUNT; ++i)
8002a88: 68fb ldr r3, [r7, #12]
8002a8a: 3301 adds r3, #1
8002a8c: 60fb str r3, [r7, #12]
8002a8e: 68fb ldr r3, [r7, #12]
8002a90: 2b0d cmp r3, #13
8002a92: d9e3 bls.n 8002a5c <_ZN3sta18STM32CanController12clearFiltersEv+0xe>
}
}
}
8002a94: bf00 nop
8002a96: bf00 nop
8002a98: 3710 adds r7, #16
8002a9a: 46bd mov sp, r7
8002a9c: bd80 pop {r7, pc}
08002a9e <_ZN3sta18STM32CanController11initFiltersEv>:
void STM32CanController::initFilters()
{
8002a9e: b480 push {r7}
8002aa0: b085 sub sp, #20
8002aa2: af00 add r7, sp, #0
8002aa4: 6078 str r0, [r7, #4]
for (uint32_t i = 0; i < MAX_FILTER_COUNT; ++i)
8002aa6: 2300 movs r3, #0
8002aa8: 60fb str r3, [r7, #12]
8002aaa: e01a b.n 8002ae2 <_ZN3sta18STM32CanController11initFiltersEv+0x44>
{
CAN_FilterTypeDef * config = &filters_[i];
8002aac: 68fa ldr r2, [r7, #12]
8002aae: 4613 mov r3, r2
8002ab0: 009b lsls r3, r3, #2
8002ab2: 4413 add r3, r2
8002ab4: 00db lsls r3, r3, #3
8002ab6: 3308 adds r3, #8
8002ab8: 687a ldr r2, [r7, #4]
8002aba: 4413 add r3, r2
8002abc: 60bb str r3, [r7, #8]
config->FilterBank = i;
8002abe: 68bb ldr r3, [r7, #8]
8002ac0: 68fa ldr r2, [r7, #12]
8002ac2: 615a str r2, [r3, #20]
config->FilterMode = CAN_FILTERMODE_IDMASK;
8002ac4: 68bb ldr r3, [r7, #8]
8002ac6: 2200 movs r2, #0
8002ac8: 619a str r2, [r3, #24]
config->FilterScale = CAN_FILTERSCALE_32BIT;
8002aca: 68bb ldr r3, [r7, #8]
8002acc: 2201 movs r2, #1
8002ace: 61da str r2, [r3, #28]
config->FilterActivation = CAN_FILTER_DISABLE;
8002ad0: 68bb ldr r3, [r7, #8]
8002ad2: 2200 movs r2, #0
8002ad4: 621a str r2, [r3, #32]
config->SlaveStartFilterBank = MAX_FILTER_COUNT;
8002ad6: 68bb ldr r3, [r7, #8]
8002ad8: 220e movs r2, #14
8002ada: 625a str r2, [r3, #36] ; 0x24
for (uint32_t i = 0; i < MAX_FILTER_COUNT; ++i)
8002adc: 68fb ldr r3, [r7, #12]
8002ade: 3301 adds r3, #1
8002ae0: 60fb str r3, [r7, #12]
8002ae2: 68fb ldr r3, [r7, #12]
8002ae4: 2b0d cmp r3, #13
8002ae6: d9e1 bls.n 8002aac <_ZN3sta18STM32CanController11initFiltersEv+0xe>
}
}
8002ae8: bf00 nop
8002aea: bf00 nop
8002aec: 3714 adds r7, #20
8002aee: 46bd mov sp, r7
8002af0: f85d 7b04 ldr.w r7, [sp], #4
8002af4: 4770 bx lr
08002af6 <_ZN3sta18STM32CanController17getPendingRxFifosEv>:
CanPendingRxFifos STM32CanController::getPendingRxFifos(){
8002af6: b580 push {r7, lr}
8002af8: b082 sub sp, #8
8002afa: af00 add r7, sp, #0
8002afc: 6078 str r0, [r7, #4]
8002afe: 6039 str r1, [r7, #0]
CanPendingRxFifos pendingFifos(42, 3);
8002b00: 2203 movs r2, #3
8002b02: 212a movs r1, #42 ; 0x2a
8002b04: 6878 ldr r0, [r7, #4]
8002b06: f7ff fdf5 bl 80026f4 <_ZN3sta17CanPendingRxFifosC1Emh>
// Example implementation:
//pendingFifos.fifo0Pending = HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO0) != 0;
//pendingFifos.fifo1Pending = HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO1) != 0;
return pendingFifos;
8002b0a: bf00 nop
}
8002b0c: 6878 ldr r0, [r7, #4]
8002b0e: 3708 adds r7, #8
8002b10: 46bd mov sp, r7
8002b12: bd80 pop {r7, pc}
08002b14 <_ZNK3sta18STM32CanController14maxFilterCountEv>:
uint8_t STM32CanController::maxFilterCount() const{
8002b14: b480 push {r7}
8002b16: b083 sub sp, #12
8002b18: af00 add r7, sp, #0
8002b1a: 6078 str r0, [r7, #4]
return MAX_FILTER_COUNT;
8002b1c: 230e movs r3, #14
}
8002b1e: 4618 mov r0, r3
8002b20: 370c adds r7, #12
8002b22: 46bd mov sp, r7
8002b24: f85d 7b04 ldr.w r7, [sp], #4
8002b28: 4770 bx lr
08002b2a <_ZNK3sta18STM32CanController12maxFifoCountEv>:
uint8_t STM32CanController::maxFifoCount() const {
8002b2a: b480 push {r7}
8002b2c: b083 sub sp, #12
8002b2e: af00 add r7, sp, #0
8002b30: 6078 str r0, [r7, #4]
return MAX_FIFO_COUNT;
8002b32: 2302 movs r3, #2
}
8002b34: 4618 mov r0, r3
8002b36: 370c adds r7, #12
8002b38: 46bd mov sp, r7
8002b3a: f85d 7b04 ldr.w r7, [sp], #4
8002b3e: 4770 bx lr
08002b40 <_ZNK3sta18STM32CanController14maxPayloadSizeEv>:
uint8_t STM32CanController::maxPayloadSize() const {
8002b40: b480 push {r7}
8002b42: b083 sub sp, #12
8002b44: af00 add r7, sp, #0
8002b46: 6078 str r0, [r7, #4]
return MAX_PAYLOAD_SIZE;
8002b48: 2308 movs r3, #8
}
8002b4a: 4618 mov r0, r3
8002b4c: 370c adds r7, #12
8002b4e: 46bd mov sp, r7
8002b50: f85d 7b04 ldr.w r7, [sp], #4
8002b54: 4770 bx lr
08002b56 <memset>:
8002b56: 4402 add r2, r0
8002b58: 4603 mov r3, r0
8002b5a: 4293 cmp r3, r2
8002b5c: d100 bne.n 8002b60 <memset+0xa>
8002b5e: 4770 bx lr
8002b60: f803 1b01 strb.w r1, [r3], #1
8002b64: e7f9 b.n 8002b5a <memset+0x4>
...
08002b68 <__libc_init_array>:
8002b68: b570 push {r4, r5, r6, lr}
8002b6a: 4d0d ldr r5, [pc, #52] ; (8002ba0 <__libc_init_array+0x38>)
8002b6c: 4c0d ldr r4, [pc, #52] ; (8002ba4 <__libc_init_array+0x3c>)
8002b6e: 1b64 subs r4, r4, r5
8002b70: 10a4 asrs r4, r4, #2
8002b72: 2600 movs r6, #0
8002b74: 42a6 cmp r6, r4
8002b76: d109 bne.n 8002b8c <__libc_init_array+0x24>
8002b78: 4d0b ldr r5, [pc, #44] ; (8002ba8 <__libc_init_array+0x40>)
8002b7a: 4c0c ldr r4, [pc, #48] ; (8002bac <__libc_init_array+0x44>)
8002b7c: f000 f818 bl 8002bb0 <_init>
8002b80: 1b64 subs r4, r4, r5
8002b82: 10a4 asrs r4, r4, #2
8002b84: 2600 movs r6, #0
8002b86: 42a6 cmp r6, r4
8002b88: d105 bne.n 8002b96 <__libc_init_array+0x2e>
8002b8a: bd70 pop {r4, r5, r6, pc}
8002b8c: f855 3b04 ldr.w r3, [r5], #4
8002b90: 4798 blx r3
8002b92: 3601 adds r6, #1
8002b94: e7ee b.n 8002b74 <__libc_init_array+0xc>
8002b96: f855 3b04 ldr.w r3, [r5], #4
8002b9a: 4798 blx r3
8002b9c: 3601 adds r6, #1
8002b9e: e7f2 b.n 8002b86 <__libc_init_array+0x1e>
8002ba0: 08002ca4 .word 0x08002ca4
8002ba4: 08002ca4 .word 0x08002ca4
8002ba8: 08002ca4 .word 0x08002ca4
8002bac: 08002ca8 .word 0x08002ca8
08002bb0 <_init>:
8002bb0: b5f8 push {r3, r4, r5, r6, r7, lr}
8002bb2: bf00 nop
8002bb4: bcf8 pop {r3, r4, r5, r6, r7}
8002bb6: bc08 pop {r3}
8002bb8: 469e mov lr, r3
8002bba: 4770 bx lr
08002bbc <_fini>:
8002bbc: b5f8 push {r3, r4, r5, r6, r7, lr}
8002bbe: bf00 nop
8002bc0: bcf8 pop {r3, r4, r5, r6, r7}
8002bc2: bc08 pop {r3}
8002bc4: 469e mov lr, r3
8002bc6: 4770 bx lr
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